PRELIMINARY
FEMTOCLOCKS™ VCXO BASED
FREQUENCY TRANSLATOR/JITTER ATTENUATOR
ICS843002-31
G
ENERAL
D
ESCRIPTION
The ICS843002-31 is a member of the
HiperClockS™ family of high performance clock
HiPerClockS™
solutions from IDT. This monolithic device is a high-
perfor mance, PLL-based synchronous clock
generator and jitter attenuation circuit. The
ICS843002-31 contains two clock multiplication stages that are
cascaded in series. The first stage is a VCXO-based PLL that
is optimized to provide reference clock jitter attenuation, to be
jitter tolerant, and to provide a stable reference clock for the
second multiplication stage. The second stage is the proprietary
IDT FemtoClock™circuit which is a high-frequency, sub-
picosecond clock multiplier.
F
EATURES
•
Outputs:
•
Two high frequency differential LVPECL outputs
Output frequency: up to 700MHz
•
One LVCMOS/LVTTL VCXO PLL output with output enable
•
One Reference clock output with output enable
•
One LOCK detect output
•
Input mux supports 3 selectable inputs: one differential input
pair and two LVCMOS/LVTTL input clocks
•
13-bit VCXO PLL feedback and reference dividers provide
wide range of frequency translation ratio options
•
FemtoClock frequency multiplier supports rate of:
560MHz - 700MHz
•
‘Lock Detect’ output reports lock status of VCXO PLL
•
VCXO PLL circuit provides jitter attenuation with
loop bandwidth of 250Hz and below (user adjustable)
•
RMS phase jitter, random at 12kHz to 20MHz:
<1ps (design target)
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
V
CCA
_
XO
XTAL_IN
XTAL_OUT
IC
S
The VCXO PLL has an on-chip VCXO circuit that uses an
external, inexpensive pullable crystal in the 17.5 to 25MHz
range. The PLL includes 13 bit reference and feedback
dividers suppor ting complex PLL multiplication ratios and
input reference clock rates as low as 2.3kHz. External loop
filter components are used (two resistors and two capacitors)
to achieve the low loop bandwidth needed for jitter atten-
uation of a recovered data clock.
The FemtoClock circuit can multiply the VCXO crystal frequency
by a factor of 28 or 32 (selectable) and provide a clock output of
up to 700MHz.
Clock Input/Output Configuration:
• Clock Inputs - one differential pair, two singled ended
(mux selected)
• Differential input pair can support LVPECL, LVDS,
LVHSTL, SSTL, HCSL or single-ended LVCMOS
or LVTTL levels
• Singled ended inputs can support LVCMOS or
LVTTL levels
• Clock Outputs, FemtoClockS two LVPECL pairs
(selectable output dividers)
• Clock Output, VCXO – one single ended output
(at VCXO crystal frequency)
• Clock Output, other – VCXO reference clock
Example Applications:
• SONET/SDH line card clock generator (up to 622.08MHz
for OC-48) using 8kHz frame clock as input reference
• Jitter attenuation of a recovered communications clock
• Complex-ratio clock frequency translation between
various communication protocols, such as:
• For telecom, OC-12 to E3 rate conversion, 622.08MHz
to 34.368MHz, PLL ratio of 179/32
• For digital video, ITU-R601 to SMPTE 252M/59.94,
27MHz to 74.17582MHz, PLL ratio of 250/91
P
IN
A
SSIGNMENT
XOFB0
XOFB1
XOFB2
XOFB3
XOFB4
XOFB5
XOFB6
XOFB7
XOFB8
XOFB9
XOFB10
XOFB11
LF1
LF0
ISET
V
EE
NV1
NV0
V
CC
MR
CLK0
nCLK0
OE_REF
CLK1
V
CC
SEL1
SEL0
CLK2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
64-Lead TQFP, EPAD
8
10mm x 10mm x 1.0mm
9
package body
10
Y package
11
XOFB12
ICS843002-31
12
13
14
Top View
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
EE
REF_CLK
VCLK
LOCK
V
CCO
_
CMOS
nQB
QB
V
EE
nQA
QA
V
CCO
_
PECL
MP
NPB0
NPB1
NPB2
V
CCA
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
1
XOIN12
XOIN11
XOIN10
XOIN9
XOIN8
XOIN7
XOIN6
XOIN5
XOIN4
XOIN3
XOIN2
XOIN1
XOIN0
NPA2
NPA1
NPA0
ICS843002BY-31
REV. C
February 23,
2009
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
(
CONTINUED ON NEXT PAGE
)
Number
1, 2
3
4, 41, 48
5, 6
7, 13
8
9
10
11
12
14, 15
16
17, 18,
19, 20,
21, 22,
23, 24,
25, 26,
27, 28
29
30, 31,
32
33
34, 35,
36
37
38,
39, 40
42, 43
44
45
46
47
Name
LF1, LF0
ISET
V
EE
NV1, NV0
V
CC
MR
CLK0
nCLK0
OE_REF
CLK1
SEL1, SEL0
CLK2
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Input
Input
Input
Input
Input
Input
Input
Description
Loop filter connection pins.
Charge pump current setting pin.
Negative supply pins. Normally connected to ground.
VCXO PLL output divider control pins.
Pullup
LVCMOS/LVTTL interface levels.
Core power supply pins.
Master Reset. When HIGH, resets all internal dividers and
Pulldown LVCMOS outputs are in high impedance.
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup/ Inver ting differential clock input.
Pulldown V
CC
/2 bias voltage when left floating.
Output enable control for reference clock output. When logic LOW,
Pulldown the reference clock output is in high impedance. When logic HIGH,
the output is enabled. LVCMOS/LVTTL interface levels.
Pulldown Clock input. LVCMOS/LVTTL interface levels.
Pulldown Input clock select. LVCMOS/LVTTL interface levels.
Pulldown Clock input. LVCMOS/LVTTL interface levels.
XOIN12:XOIN1
Input
Pulldown
VCXO PLL input divider control input.
LVCMOS/LVTTL interface levels.
XOIN0
NPA2, NPA1,
NPA0
V
CCA
NPB2, NPB1,
NPB0
MP
V
CCO_PECL
QA, nQA
QB, nQB
V
CCO_CMOS
LOCK
VCLK
REF_CLK
Input
Input
Power
Input
Input
Power
Output
Output
Power
Output
Output
Output
VCXO PLL input divider control input.
LVCMOS/LVTTL interface levels.
LVPECL output divider control for QA/nQA outputs.
Pulldown
LVCMOS/LVTTL interface levels.
Analog supply pin.
LVPECL output divider control for QB/nQB outputs.
Pulldown
LVCMOS/LVTTL interface levels.
FemtoClock™ circuit clock multiplication control input.
Pulldown When HIGH, selects 28. When LOW, selects 32.
LVCMOS/LVTTL interface levels.
Output power supply pin for LVPECL clock outputs.
Pullup
Differential clock output pair. LVPECL interface levels.
Differential clock output pair. LVPECL interface levels.
Output power supply pin for LVCMOS outputs.
Lock detect output. LVCMOS/LVTTL interface levels.
VCXO PLL clock output. LVCMOS/LVTTL interface levels.
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT
™
/ ICS
™
VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
4
ICS843002BY-31 REV. C February 23, 2009
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EEWORLD
