DATA SHEET
LOW SKEW,
BUFFER
Integrated
1-TO-4 DIFFERENTIAL-TO-HSTL
Circuit
Systems, Inc.
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
FANOUT
ICS8523
ICS8523
G
ENERAL
D
ESCRIPTION
The ICS8523 is a low skew, high perfor-
mance 1-to-4 Differential-to-HSTL fanout buffer
HiPerClockS™
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8523 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
F
EATURES
•
4 differential HSTL compatible outputs
•
Selectable diffferential CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency: 650MHz
•
Translates any single-ended input signal to HSTL
levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 200ps (maximum)
•
Propagation delay: 1.6ns (maximum)
•
3.3V core, 1.8V output operating supply
•
0°C to 70°C ambient operating temperature
•
Lead-Free package available
•
Industrial temperature information available upon request
ICS
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK
nCLK
PCLK
nPCLK
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
CLK_SEL
ICS8523
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
8523BG
www.icst.com/products/hiperclocks.html
1
REV. D SEPTEMBER 13, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
1
ICS8523
ICS8523
Circuit
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
ICS8523
L
OW
S
KEW
, 1-
TO
-4
TSD
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
Systems, Inc.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
Name
GND
CLK_EN
Power
Input
Type
Description
3
4
5
6
7
8, 9
10
11, 12
13, 18
14, 15
16, 17
19, 20
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
V
DD
nQ3, Q3
V
DDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Unused
Power
Output
Power
Output
Output
Output
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q outputs are forced low, nQ outputs are forced
Pullup
high. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential PCLK, nPCLK
Pulldown inputs. When LOW, selects CLK, nCLK inputs.
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Pullup
Inver ting differential clock input.
Inver ting differential LVPECL clock input.
No connect.
Core supply pin.
Differential output pair. HSTL interface levels.
Output supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8523BG
www.icst.com/products/hiperclocks.html
2
REV. D SEPTEMBER 13, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
2
ICS8523
ICS8523
Circuit
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
ICS8523
L
OW
S
KEW
, 1-
TO
-4
TSD
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
Outputs
Systems, Inc.
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
CLK_SEL
0
1
0
Selected Source
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Disabled
Enabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK or nPCLK
0
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ3
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8523BG
www.icst.com/products/hiperclocks.html
3
REV. D SEPTEMBER 13, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3
ICS8523
ICS8523
Circuit
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
ICS8523
L
OW
S
KEW
, 1-
TO
-4
TSD
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Systems, Inc.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
50
Units
V
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_EN, CLK_SEL
CLK_EN, CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8523BG
www.icst.com/products/hiperclocks.html
4
REV. D SEPTEMBER 13, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
4
ICS8523
ICS8523
Circuit
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
ICS8523
L
OW
S
KEW
, 1-
TO
-4
TSD
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
Minimum
Typical
Maximum
150
5
-5
-150
0.3
1
V
DD
Units
µA
µA
µA
µA
V
V
Systems, Inc.
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
PCLK
nPCLK
PCLK
nPCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
1.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is V
DD
+ 0.3V.
T
ABLE
4D. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
Output High Voltage;
V
OH
NOTE 1
Output Low Voltage;
V
OL
NOTE 1
V
OX
V
SWING
Output Crossover Voltage
Test Conditions
Minimum
0.9
0
40% x (V
OH
- V
OL
) + V
OL
0.75
Typical
Maximum
1.4
0.4
60% x (V
OH
- V
OL
) + V
OL
1.25
Units
V
V
V
V
Peak-to-Peak
Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to ground.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
IJ 650MHz
1.0
Test Conditions
Minimum
Typical
Maximum
650
1.6
30
200
700
700
55
Units
MHz
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
45
All parameters measured at 500MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8523BG
www.icst.com/products/hiperclocks.html
5
REV. D SEPTEMBER 13, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
5
ICS8523
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