EMBEDDED ULTRA-LOW POWER Intel486
™
GX PROCESSOR
■
Ultra-Low Power Member of the Intel486™
■
16-Bit External Data Bus
Processor Family
■
— 32-Bit RISC Technology Core
■
— 8-Kbyte Write-Through Cache
■
— Four Internal Write Buffers
■
— Burst Bus Cycles
— Data Bus Parity Generation and
■
Checking
— Intel System Management Mode (SMM)
— Boundary Scan (JTAG)
176-Lead Thin Quad Flat Pack (TQFP)
Separate Voltage Supply for Core Circuitry
Fast Core-Clock Restart
Auto Clock Freeze
Ideal for Embedded Battery-Operated and
Hand-Held Applications
64-Bit Interunit Transfer Bus
32-Bit Data Bus
32-Bit Data Bus
Linear Address
32
32
32
PCD
PWT
Core
Clock
Clock
Control
CLK Input
Barrel
Shifter
Register
File
ALU
Base/
Index
Bus
32
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
2
Bus Interface
Paging
Unit
Cache Unit
20
Physical
Address
8 Kbyte
Cache
32
Address
Drivers
Write Buffers
4 x 32
Data Bus
32 Transceivers
Bus Control
A31-A2
BE3#- BE0#
Translation
Lookaside
Buffer
32
D15-D0
128
Displacement Bus
32
Prefetcher
Micro-
Instruction
32-Byte Code
Queue
2x16 Bytes
Request
Sequencer
ADS# W/R# D/C# M/IO#
PCD PWT RDY# LOCK#
PLOCK# BOFF# A20M#
BREQ HOLD HLDA
RESET SRESET INTR
NMI SMI# SMIACT#
STPCLK#
Control &
Protection
Test Unit
Code
Stream
Instruction
Decode
Decoded
Instruction
Path
24
BRDY# BLAST#
Burst Bus
Control
Control
ROM
Parity
Generation
and Control
Cache
Control
Boundary
Scan
Control
DP1-DP0, PCHK#
KEN# FLUSH#
AHOLD EADS#
TCK TMS
TDI TD0
A5851-01
Figure 1. Embedded Ultra-Low Power Intel486™ GX Processor Block Diagram
© INTEL CORPORATION, 1997
December 1997
Order Number:
272755-002
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The Embedded Ultra-Low Power Intel486™ GX processor may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current characterized errata are
available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1997
*Third-party brands and names are the property of their respective owners.
Contents
Embedded Ultra-Low Power Intel486
™
GX Processor
1.0 INTRODUCTION ........................................................................................................................................ 1
1.1 Features ............................................................................................................................................. 1
1.2 Family Members ................................................................................................................................. 3
2.0 HOW TO USE THIS DOCUMENT ............................................................................................................. 3
3.0 PIN DESCRIPTIONS ................................................................................................................................. 3
3.1 Pin Assignments ................................................................................................................................. 3
3.2 Pin Quick Reference ........................................................................................................................... 7
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 15
Separate Supply Voltages ................................................................................................................ 15
Fast Clock Restart ............................................................................................................................ 16
Level-Keeper Circuits ....................................................................................................................... 17
Low-Power Features ........................................................................................................................ 18
4.4.1 Auto Clock Freeze ................................................................................................................. 18
4.5 Bus Interface and Operation ............................................................................................................. 19
4.5.1 16-Bit Data Bus ...................................................................................................................... 19
4.5.2 Parity ...................................................................................................................................... 19
4.5.3 Data Transfer Mechanism ...................................................................................................... 19
4.6 CPUID Instruction ............................................................................................................................. 27
4.6.1 Operation of the CPUID Instruction ....................................................................................... 27
4.7 Identification After Reset .................................................................................................................. 29
4.8 Boundary Scan (JTAG) .................................................................................................................... 29
4.8.1 Device Identification ............................................................................................................... 29
4.8.2 Boundary Scan Register Bits and Bit Order ........................................................................... 29
5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 30
5.1 Maximum Ratings ............................................................................................................................. 30
5.2 DC Specifications ............................................................................................................................. 30
5.3 AC Specifications ............................................................................................................................. 34
5.4 Capacitive Derating Curves .............................................................................................................. 41
6.0 MECHANICAL DATA .............................................................................................................................. 42
6.1 Package Dimensions ........................................................................................................................ 42
6.2 Package Thermal Specifications ...................................................................................................... 43
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Embedded Ultra-Low Power Intel486™ GX Processor Block Diagram ...................................... i
Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486™ GX Processor .... 4
Example of Supply Voltage Power Sequence ......................................................................... 16
Stop Clock State Diagram with Typical Power Consumption Values ...................................... 17
Logic to Generate A1, BHE# and BLE# ................................................................................... 19
4.1
4.2
4.3
4.4
iii
Contents
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Address Prediction for Burst Transfers (1 of 3) ........................................................................ 25
Address Prediction for Burst Transfers (2 of 3) ........................................................................ 26
Address Prediction for Burst Transfers (3 of 3) ........................................................................ 27
CLK Waveform ......................................................................................................................... 37
Input Setup and Hold Timing ................................................................................................... 37
Input Setup and Hold Timing ................................................................................................... 38
Output Valid Delay Timing ....................................................................................................... 38
PCHK# Valid Delay Timing ...................................................................................................... 39
Maximum Float Delay Timing .................................................................................................. 39
TCK Waveform ........................................................................................................................ 40
Test Signal Timing Diagram ..................................................................................................... 40
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition ..................................................................................................... 41
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition ..................................................................................................... 41
Package Mechanical Specifications for the 176-Lead TQFP Package .................................... 42
The Embedded Ultra-Low Power Intel486
™
GX Processor ....................................................... 3
Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486™ GX Processor ........ 5
Pin Cross Reference for 176-Lead TQFP Package Embedded ULP
Intel486™ GX Processor ........................................................................................................... 6
Embedded ULP Intel486™ GX Processor Pin Descriptions ...................................................... 7
Output Pins .............................................................................................................................. 13
Input/Output Pins ..................................................................................................................... 13
Test Pins .................................................................................................................................. 14
Input Pins ................................................................................................................................. 14
Valid Byte-Enable Cycles ......................................................................................................... 20
Address Sequence for Cache Line Transfers and Instruction Prefetches ............................... 22
Valid Burst Cycle Sequences - I/O Reads and All Writes ........................................................ 23
CPUID Instruction Description ................................................................................................. 28
Boundary Scan Component Identification Code ...................................................................... 29
Absolute Maximum Ratings ..................................................................................................... 30
Operating Supply Voltages ...................................................................................................... 31
DC Specifications ..................................................................................................................... 31
Active I
CC
Values ..................................................................................................................... 32
Clock Stop, Stop Grant, and Auto HALT Power Down I
CC
Values .......................................... 33
AC Characteristics ................................................................................................................... 34
AC Specifications for the Test Access Port ............................................................................. 36
Thermal Resistance ................................................................................................................. 43
Maximum Ambient Temperature (T
A
) ...................................................................................... 43
iv
Embedded Ultra-Low Power Intel486™ GX Processor
1.0
INTRODUCTION
This data sheet describes the embedded Ultra-Low
Power (ULP) Intel486™ GX processor. It is intended
for embedded battery-operated and hand-held appli-
cations. The embedded ULP Intel486 GX processor
provides all of the features of the Intel486 SX
processor except for the 8-bit bus sizing logic and
the processor-upgrade pin. The processor typically
uses 20% to 50% less power than the Intel486 SX
processor. Additionally, the embedded ULP Intel486
GX processor external data bus and parity signals
have level-keeper circuitry and a fast-recovery core
clock which are vital for ultra-low-power system
designs. The processor is available in a Thin Quad
Flat
Package
(TQFP)
enabling
low-profile
component implementation.
The embedded ULP Intel486 GX processor consists
of a 32-bit integer processing unit, an on-chip cache,
and a memory management unit. The design
ensures full instruction-set compatibility with the
8086, 8088, 80186, 80286, Intel386™ SX, Intel386
DX, and all versions of Intel486 processors.
1.1
Features
The embedded ULP Intel486 GX processor offers
these features of the Intel486 SX processor:
•
32-bit RISC-Technology Core
— The embedded
ULP Intel486 GX processor performs a complete
set of arithmetic and logical operations on 8-, 16-,
and 32-bit data types using a full-width ALU and
eight general purpose registers.
•
Single Cycle Execution
— Many instructions
execute in a single clock cycle.
•
Instruction Pipelining
— Overlapped instruction
fetching, decoding, address translation and
execution.
•
On-Chip Cache with Cache Consistency
Support —
An 8-Kbyte, write-through, internal
cache is used for both data and instructions.
Cache hits provide zero wait-state access times
for data within the cache. Bus activity is tracked to
detect alterations in the memory represented by
the internal cache. The internal cache can be
invalidated or flushed so that an external cache
controller can maintain cache consistency.
•
External Cache Control
— Write-back and flush
controls for an external cache are provided so the
processor can maintain cache consistency.
•
On-Chip Memory Management Unit
— Address
management and memory space protection
mechanisms maintain the integrity of memory in a
multitasking and virtual memory environment. Both
segmentation and paging are supported.
•
Burst Cycles
— Burst transfers allow a new 16-bit
data word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache. Burst transfers also occur on some
memory write and some I/O data transfers.
•
Write Buffers
— The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.
•
Bus Backoff
— When another bus master needs
control of the bus during a processor initiated bus
cycle, the embedded ULP Intel486 GX processor
floats its bus signals, then restarts the cycle when
the bus becomes available again.
•
Instruction Restart
— Programs can continue
execution following an exception generated by an
unsuccessful attempt to access memory. This
feature is important for supporting demand-paged
virtual memory applications.
•
Boundary Scan (JTAG)
— Boundary Scan
provides in-circuit testing of components on
printed circuit boards. The Intel Boundary Scan
implementation conforms with the IEEE Standard
Test Access Port and Boundary Scan Architecture.
1
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