CY7C419/21/25/29/33256/512/1K/2K/4K x 9 Asynchronous FIFO
CY7C419/21/25/29/33
256/512/1K/2K/4K x 9 Asynchronous FIFO
Features
• Asynchronous first-in first-out (FIFO) buffer memories
• 256 x 9 (CY7C419)
• 512 x 9 (CY7C421)
• 1K x 9 (CY7C425)
• 2K x 9 (CY7C429)
• 4K x 9 (CY7C433)
• Dual-ported RAM cell
• High-speed 50.0-MHz read/write independent of
depth/width
• Low operating power: I
CC
= 35 mA
• Empty and Full flags (Half Full flag in standalone)
• TTL compatible
• Retransmit in standalone
• Expandable in width
• PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP
• Pb-Free Packages Available
• Pin compatible and functionally equivalent to IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
600-mil wide and 300-mil wide packages. They are, respec-
tively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide.
Each FIFO memory is organized such that the data is read in
the same sequential order that it was written. Full and Empty
flags are provided to prevent overrun and underrun. Three
additional pins are also provided to facilitate unlimited
expansion in width, depth, or both. The depth expansion
technique steers the control signals from one device to
another in parallel, thus eliminating the serial addition of
propagation delays, so that throughput is not reduced. Data is
steered in a similar manner.
The read and write operations may be asynchronous; each
can occur at a rate of 50.0 MHz. The write operation occurs
when the write (W) signal is LOW. Read occurs when read (R)
goes LOW. The nine data outputs go to the high-impedance
state when R is HIGH.
A Half Full (HF) output flag is provided that is valid in the
standalone and width expansion configurations. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it will be
activated.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable (W) must both be
HIGH during retransmit, and then R is used to access the data.
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated
using an advanced 0.65-micron P-well CMOS technology.
Input ESD protection is greater than 2000V and latch-up is
prevented by careful layout and guard rings.
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
Cypress Semiconductor Corporation
Document #: 38-06001 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised June 30, 2005
CY7C419/21/25/29/33
Logic Block Diagram
DATA INPUTS
(D0–D 8)
Pin Configurations
PLCC/LCC
Top View
D
3
D
8
W
NC
V
cc
D
4
D
5
4 3 2 1 323130
5
29
6
28
7
27
8
26
7C419
7C421/5/9 25
9
7C433
10
24
11
23
12
22
13
21
14 15 1617 181920
Q
3
Q
8
GND
NC
R
Q
4
Q
5
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
DIP
Top View
1
28
2
27
3
26
4
25
5
24
7C419
6 7C420/1 23
7 7C424/5 22
8 7C428/9 21
7C432/3
9
20
10
19
11
18
12
17
13
16
15
14
Vcc
D
4
D
5
D
6
D
7
FL/RT
MR
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
W
WRITE
CONTROL
WRITE
POINTER
RAM ARRAY
256 x 9
512 x 9
1024x 9
2048x 9
4096x 9
READ
POINTER
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
D
6
D
7
NC
FL/RT
MR
EF
XO/HF
Q
7
Q
6
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q0–Q 8)
R
READ
CONTROL
FLAG
LOGIC
RESET
LOGIC
MR
FL/RT
TQFP
Top View
D
3
D
8
W
V
CC
D
4
D
2
EF
FF
32 3130 29 28 27 26 25
D
1
D
0
NC
NC
XI
FF
Q
0
Q
1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
D
5
D
6
D
7
FL/RT
NC
NC
MR
EF
XO/HF
Q
7
XI
EXPANSION
LOGIC
XO/HF
7C419
7C421/5/9
7C433
9 10 11 12 13 14 15 16
Q
2
Q
3
Q
8
GND
R
Q
4
Q
5
Selection Guide
256 x 9
512 x 9 (600-mil only)
512 x 9
1K x 9 (600-mil only)
1K x 9
2K x 9 (600-mil only)
2K x 9
4K x 9 (600-mil only)
4K x 9
Frequency (MHz)
Maximum Access Time (ns)
I
CC1
(mA)
7C433–10
50
10
35
7C433–15
40
15
35
7C433–20
33.3
20
35
7C429–10
7C429–15
7C425–10
7C425–15
7C421–10
7C421–15
7C419–10
7C419–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C429–25
7C432–25
7C433–25
28.5
25
35
7C433–30
25
30
35
7C429–30
7C429–40
7C432–40
7C433–40
20
40
35
7C433–65
12.5
65
35
7C420–25
7C421–25
7C424–25
7C425–25
7C421–30
7C424–30
7C425–30
7C419–30
7C419–40
7C420–40
7C421–40
7C424–40
7C425–40
7C420–65
7C421–65
7C424–65
7C425–65
7C428–65
7C429–65
Maximum Rating
[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Power Dissipation.......................................................... 1.0W
Output Current, into Outputs (LOW)............................ 20 mA
Static Discharge Voltage............................................ >2000V
(per MIL–STD–883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Note:
1. Single Power Supply: The voltage on any input or I/O pin can not exceed the power pin during power-up.
Document #: 38-06001 Rev. *B
Q
6
Page 2 of 25
CY7C419/21/25/29/33
Operating Range
Range
Commercial
Industrial
Military
Ambient Temperature
[2]
0
°
C to + 70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[3]
7C419–10, 15, 30, 40
7C420/1–10, 15, 20, 25, 30, 40, 65
7C424/5–10, 15, 20, 25, 30, 40, 65
7C428/9–10, 15, 20, 25, 30, 40, 65
7C432/3–10, 15, 20, 25, 30, 40, 65
Min.
Max.
2.4
0.4
2.0
V
CC
2.2
V
CC
Note 4
0.8
–10
+10
–10
+10
–90
Parameter
Description
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
V
IH
Input HIGH Voltage
V
IL
I
IX
I
OZ
I
OS
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Output Short Circuit Current
[5]
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Com’l
Mil/Ind
GND < V
I
< V
CC
R > V
IH
, GND < V
O
< V
CC
V
CC
= Max., V
OUT
= GND
Unit
V
V
V
V
µA
µA
mA
Electrical Characteristics
Over the Operating Range
[3]
(continued)
7C419–10
7C421–10
7C425–10
7C429–10
7C433–10
Parameter
I
CC
Description
Operating Current
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA
f = f
MAX
V
CC
= Max.,
I
OUT
= 0 mA
F = 20 MHz
All Inputs =
V
IH
Min.
Com’l
Mil/Ind
Com’l
35
85
7C419–15
7C421–15
7C425–15
7C429–15
7C433–15
65
100
35
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C433–20
55
90
35
7C420–25
7C421–25
7C424–25
7C425–25
7C429–25
7C432–25
7C433–25
Unit
mA
50
80
35
mA
Min. Max. Min. Max. Min. Max. Min. Max.
I
CC1
Operating Current
I
SB1
I
SB2
Standby Current
Com’l
Mil/Ind
Com’l
Mil/Ind
10
5
10
15
5
8
10
15
5
8
10
15
5
8
mA
mA
Power-Down Current All Inputs >
V
CC
–0.2V
Notes:
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. V
IL
(Min.) = –2.0V for pulse durations of less than 20 ns.
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-06001 Rev. *B
Page 3 of 25
CY7C419/21/25/29/33
Switching Characteristics
Over the Operating Range
[7, 8]
7C419–10
7C421–10
7C425–10
7C429–10
7C433–10
Parameter
t
RC
t
A
t
RR
t
PR
t
LZR
[6,9]
[9,10]
7C419–15
7C421–15
7C425–15
7C429–15
7C433–15
Min.
25
Max.
15
10
15
3
5
10
20
3
5
15
25
15
5
10
8
0
25
15
10
15
15
25
15
10
30
20
5
10
12
0
30
20
10
20
20
30
20
10
15
35
25
5
10
15
0
35
25
10
25
25
35
25
10
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C433–20
Min.
30
20
10
25
3
5
18
Max.
7C420–25
7C421–25
7C424–25
7C425–25
7C429–25
7C432–25
7C433–25
Min.
35
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read LOW to Low Z
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
Write Pulse Width
Write HIGH to Low Z
Write Recovery Time
Data Set-Up Time
Data Hold Time
MR Cycle Time
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
Min.
20
Max.
10
10
10
3
5
15
20
10
5
10
6
0
20
10
10
10
10
20
10
10
t
DVR
t
WC
t
PW
t
HZR[6,9,10]
t
HWZ[6,9]
t
WR
t
SD
t
HD
t
MRSC
t
PMR
t
RMR
t
RPW
t
WPW
t
RTC
t
PRT
t
RTR
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified I
OL
/I
OH
and 30 pF load
capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
8. See the last page of this specification for Group A subgroup testing information.
9. t
HZR
transition is measured at +200 mV from V
OL
and –200 mV from V
OH
. t
DVR
transition is measured at the 1.5V level. t
HWZ
and t
LZR
transition is measured
at
±100
mV from the steady state.
10. t
HZR
and t
DVR
use capacitance loading as in part (b) of AC Test Load and Waveforms.
Document #: 38-06001 Rev. *B
Page 5 of 25
Analog electronics
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