SY100S839VZI datasheet, PDF - EEWORLD Datasheet

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SY100S839VZI: DescriptionIC clock gen 3.3V/5V 20-soic; Categorysemiconductor Analog mixed-signal IC; File Size61KB，6 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY100S839VZI Overview

IC clock gen 3.3V/5V 20-soic

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Micrel, Inc.

2/4,

4/5/6 CLOCK

GENERATION CHIP

Precision Edge

SY100S839V

Precision Edge

SY100S839V

FEATURES

3.3V and 5V power supply option

50ps output-to-output skew

50% duty cycle outputs

Synchronous enable/disable

Master Reset for synchronization

Internal 75K

Ω

input pull-down resistors

Available in 20-pin SOIC package

Precision Edge

DESCRIPTION

The SY100S839V is a low skew

÷2/4, ÷4/5/6

clock

generation chip designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The device can be driven

by either a differential or single-ended ECL/LVECL or, if

positive power supplies are used, PECL/LVPECL input

signal. In addition, by using the V

output, a sinusoidal

source can be AC-coupled into the device. If a single-

ended input is to be used, the V

output should be

connected to the /CLK input and bypassed to ground via

a 0.01µF capacitor. The V

output is designed to act as

the switching reference for the input of the S839V under

single-ended input conditions. As a result, this pin can

only source/sink up to 0.5mA of current.

The common enable (/EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

Upon start-up, the internal flip-flops will attain a

random state; the master reset (MR) input must be

asserted to ensure synchronization. For systems which

only use one S839V, the MR pin need not be exercised

as the internal divider designs ensures synchronization

between the

÷2/4,

and the

÷4/5/6

outputs of a single

device.

Precision Edge is a registered trademark of Micrel, Inc.

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Rev.: B

Amendment: /0

Issue Date: March 2006

SY100S839VZI Related Products

	SY100S839VZI	SY100S839VZI TR	SY100S839VZC TR
Description	IC clock gen 3.3V/5V 20-soic	IC clock gen 3.3V/5V 20-soic	IC clock gen 3.3V/5V 20-soic

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