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About This Manual
®
Notes
Overview
This user manual includes hardware and software information on the 89HPES12NT12G2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website
(www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES12NT12G2 Device Overview,”
provides an introduction to the performance capabili-
ties of the 89HPES12NT12G2 and a high level architectural overview of the device.
Chapter 2, “Clocking,”
provides a description of the PES12NT12G2 clocking architecture.
Chapter 3, “Reset and Initialization,”
describes the PES12NT12G2 reset operations and initialization
procedure.
Chapter 4, “Switch Core,”
provides a description of the PES12NT12G2 switch core.
Chapter 5, “Switch Partitions,”
describes how the PES12NT12G2 supports up to 4 active switch parti-
tions.
Chapter 6, “Failover,”
provides a description of the flexible failover mechanism that allows the
construction of highly-available systems.
Chapter 7, “Link Operation,”
describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 8, “SerDes,”
describes basic functionality and controllability associated with the Serialiazer-
Deserializer (SerDes) block in PES12NT12G2 ports.
Chapter 9, “Power Management,”
describes the power management capability structure located in the
configuration space of each PCI-to-PCI bridge in the PES12NT12G2.
Chapter 10, “Transparent Operation,”
describes the device-specific architectural features for the
transparent switch associated with each PES12NT12G2 partition (i.e., the PCI-to-PCI bridge functions and
their interaction in the switch).
Chapter 11, “Hot-Plug and Hot-Swap,”
describes the behavior of the hot-plug and hot-swap features
in the PES12NT12G2.
Chapter 12, “SMBus Interfaces,”
describes the operation of the 2 SMBus interfaces on the
PES12NT12G2.
Chapter 13, “General Purpose I/O,”
describes how the 9 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 14, “Non-Transparent Operation,”
describes how a non-transparent bridge in the
PES12NT12G2 allows two roots or PCI Express trees (i.e., hierarchies) to be interconnected with one or
more shared address windows between them.
Chapter 15, “DMA Controller,”
describes how the PES12NT12G2 supports two direct memory access
controller (DMA) functions.
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Notes
Chapter 16, “Switch Events,”
describes mechanisms provided by the PES12NT12G2 to facilitate
communication between roots associated with different partitions as well as for communication between
these roots and a management agent.
Chapter 17, “Multicast,”
describes how the multicast capability enables a single TLP to be forwarded
to multiple destinations.
Chapter 18, “Temperature Sensor,”
provides a description of the on-chip temperature sensor with
three programmable temperature thresholds and a temperature history capability.
Chapter 19, “Register Organization,”
describes the organization of all the software visible registers in
the PES12NT12G2 and provides the address space for those registers.
Chapter 20, “PCI to PCI Bridge and Proprietary Port Specific Registers,”
lists the Type 1 configura-
tion header registers in the PES12NT12G2 and provides a description of each bit in those registers.
Chapter 21, “Proprietary Registers,”
lists the proprietary registers in the PES12NT12G2 and provides
a description of each bit in those registers.
Chapter 22, “NT Endpoint Registers,”
lists the NT Endpoint registers in the PES12NT12G2 and
provides a description of each bit in those registers.
Chapter 23, “DMA Registers,”
lists the DMA registers in the PES12NT12G2 and provides a descrip-
tion of each bit in those registers.
Chapter 24, “Switch Control Registers,”
lists the switch control and status registers in the
PES12NT12G2 and provides a description of each bit in those registers.
Chapter 25, “JTAG Boundary Scan,”
discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Chapter 26, “Usage Models,”
describes possible configurations of the PES12NT12G2 switch and
presents some important system usage models.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.
To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.
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IDT
Notes
single clock cycle
1
2
3
4
high-to-low
transition
low-to-high
transition
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[y:x]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
Data Units
The following data unit terminology is used in this document.
Term
Byte
Word
Doubleword (DWord)
Quadword (QWord)
Words
1/2
1
2
4
Bytes
1
2
4
8
Bits
8
16
32
64
Table 1 Data Unit Terminology
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
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