PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
Rev. 8 — 22 January 2014
Product data sheet
1. General description
The PCA9306 is a dual bidirectional I
2
C-bus and SMBus voltage-level translator with an
enable (EN) input, and is operational from 1.0 V to 3.6 V (V
ref(1)
) and 1.8 V to 5.5 V
(V
bias(ref)(2)
).
The PCA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the
use of a direction pin. The low ON-state resistance (R
on
) of the switch allows connections
to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,
and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,
allowing bidirectional data flow between ports. When EN is LOW, the translator switch is
off, and a high-impedance state exists between ports.
The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level
translation and physically isolates the capacitance to either side of the bus when both
sides are connected. The PCA9306 only isolates both sides when the device is disabled
and provides voltage level translation when active.
The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency
and the other at 100 kHz operating frequency. If the two buses are operating at different
frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other
bus is required. If the master is running at 400 kHz, the maximum system operating
frequency may be less than 400 kHz because of the delays added by the translator.
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector
configuration of the I
2
C-bus. The size of these pull-up resistors depends on the system,
but each side of the translator must have a pull-up resistor. The device is designed to work
with Standard-mode, Fast-mode and Fast-mode Plus I
2
C-bus devices in addition to
SMBus devices. The maximum frequency is dependent on the RC time constant, but
generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the
voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull-up supply voltage (V
pu(D)
) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2
channel.
NXP Semiconductors
PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
2-bit bidirectional translator for SDA and SCL lines in mixed-mode I
2
C-bus applications
Standard-mode, Fast-mode, and Fast-mode Plus I
2
C-bus and SMBus compatible
Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and
Fast-mode I
2
C-bus devices and multiple masters
Allows voltage level translation between:
1.0 V V
ref(1)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
bias(ref)(2)
1.2 V V
ref(1)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
bias(ref)(2)
1.8 V V
ref(1)
and 3.3 V or 5 V V
bias(ref)(2)
2.5 V V
ref(1)
and 5 V V
bias(ref)(2)
3.3 V V
ref(1)
and 5 V V
bias(ref)(2)
Provides bidirectional voltage translation with no direction pin
Low 3.5
ON-state connection between input and output ports provides less signal
distortion
Open-drain I
2
C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2)
5 V tolerant I
2
C-bus I/O ports to support mixed-mode signal operation
High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: SO8, TSSOP8, VSSOP8, XQFN8, XSON8, XSON8U
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
2 of 35
NXP Semiconductors
PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
3. Ordering information
Table 1.
Ordering information
T
amb
=
40
C to +85
C.
Type number
PCA9306D
PCA9306DC
PCA9306DC1
[1]
PCA9306DC1/DG
[2]
PCA9306DP
PCA9306DP1
[4]
PCA9306GD1
[5]
PCA9306GF
PCA9306GM
Topside
mark
PCA9306
306C
P06
P06
306P
306T
P06
06
P6X
[6]
Package
Name
SO8
VSSOP8
VSSOP8
VSSOP8
TSSOP8
[3]
TSSOP8
XSON8U
XSON8
XQFN8
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic thin shrink small outline package; 8 leads;
body width 3 mm
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3
2
0.5 mm
extremely thin small outline package; no leads; 8 terminals;
body 1.35
1
0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6
1.6
0.5 mm
Version
SOT96-1
SOT765-1
SOT765-1
SOT765-1
SOT505-1
SOT505-2
SOT996-2
SOT1089
SOT902-2
[1]
[2]
Same footprint and pinout as the Texas Instruments PCA9306DCU.
PCA9306DC1/DG is functionally the same (electrically and mechanically) as the PCA9306DC1 and the Texas Instruments
PCA9306DCT. It is produced in Dark Green (lead-free and halogen/antimony-free) package material, with a unique orderable part
number for customers who desire to order and only receive Dark Green package material.
Also known as MSOP8.
Same footprint and pinout as the Texas Instruments PCA9306DCT.
Low cost, thinner, drop-in replacement for VSSOP8 (SOT765-1) package.
‘X’ will change based on date code.
[3]
[4]
[5]
[6]
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCA9306D,112
PCA9306D,118
PCA9306DC
PCA9306DC1
PCA9306DC1/DG
PCA9306DC,125
PCA9306DC1,125
Package
Packing method
Minimum
order
quantity
Temperature
Type number
PCA9306D
SO8
SO8
VSSOP8
VSSOP8
Standard marking *
2000
IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*standard mark SMD
Reel 7” Q3/T4
*standard mark
Reel 7” Q3/T4
*standard mark
Reel 7” Q3/T4
*standard mark
2500
3000
3000
3000
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
PCA9306DC1/DG,125 VSSOP8
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
3 of 35
NXP Semiconductors
PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
Table 2.
Ordering options
…continued
Orderable
part number
PCA9306DP,118
PCA9306DP1,125
PCA9306GD1,125
PCA9306GF,115
PCA9306GM,125
Package
Packing method
Minimum
order
quantity
2500
3000
3000
5000
4000
Temperature
Type number
PCA9306DP
PCA9306DP1
PCA9306GD1
PCA9306GF
PCA9306GM
TSSOP8
TSSOP8
XSON8U
XSON8
XQFN8
Reel 13” Q1/T1
*standard mark SMD
Reel 7” Q3/T4
*standard mark
Reel 7” Q3/T4
*standard mark
Reel 7” Q1/T1
*standard mark SMD
Reel 7” Q3/T4
*standard mark
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
4. Functional diagram
VREF1
2
VREF2
7
8
6
EN
SCL2
PCA9306
SCL1
3
SW
SDA1
4
SW
5
SDA2
1
GND
002aab844
Fig 1.
Logic diagram of PCA9306 (positive logic)
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
4 of 35
NXP Semiconductors
PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
5. Pinning information
5.1 Pinning
GND
VREF1
SCL1
SDA1
1
2
3
4
002aab842
8
7
EN
VREF2
SCL2
SDA2
GND
VREF1
SCL1
SDA1
1
2
3
4
002aac373
8
7
EN
VREF2
SCL2
SDA2
PCA9306DP1
6
5
PCA9306DP
6
5
Fig 2.
Pin configuration for TSSOP8
(DP1)
Fig 3.
Pin configuration for TSSOP8 (DP)
(MSOP8)
PCA9306DC1
PCA9306DC1/DG
VREF1
SCL1
SDA1
GND
1
2
3
4
002aac374
8
EN
VREF2
SCL2
SDA2
GND
VREF1
SCL1
SDA1
1
2
3
4
002aab843
8
7
6
5
EN
VREF2
SCL2
SDA2
PCA9306DC
7
6
5
Fig 4.
Pin configuration for VSSOP8 (DC)
Fig 5.
Pin configuration for VSSOP8
(DC1; DC1/DG)
EN
1
8
terminal 1
index area
GND
7
VREF2
PCA9306GM
VREF1
GND
VREF1
SCL1
SDA1
1
2
8
7
EN
VREF2
SCL2
SDA2
SCL1
3
4
5
SDA2
2
6
SCL2
PCA9306D
SDA1
3
4
002aac372
6
5
002aac375
Transparent top view
Fig 6.
Pin configuration for SO8
Fig 7.
Pin configuration for XQFN8
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
5 of 35
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