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A1225A-PL84I

Description
fpga - field programmable gate array 2.5K system gates
CategoryProgrammable logic devices    Programmable logic   
File Size653KB,38 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Download Datasheet Parametric View All

A1225A-PL84I Overview

fpga - field programmable gate array 2.5K system gates

A1225A-PL84I Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerActel
package instructionPLASTIC, LCC-84
Reach Compliance Codecompliant
Other featuresMAX 72 I/OS
maximum clock frequency67.6 MHz
Combined latency of CLB-Max5 ns
JESD-30 codeS-PQCC-J84
JESD-609 codee0
length29.3116 mm
Humidity sensitivity level3
Configurable number of logic blocks451
Equivalent number of gates2500
Number of entries83
Number of logical units451
Output times83
Number of terminals84
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize451 CLBS, 2500 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC84,1.2SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)225
power supply5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width29.3116 mm
v4.0.1
ACT
2 Family FPGAs
Fe a t ur es
• Up to 8000 Gate Array Gates
(20,000 PLD equivalent gates)
• Replaces up to 200 TTL Packages
• Replaces up to eighty 20-Pin PAL
®
Packages
• Datapath Performance at 105 MHz
• 16-Bit Accumulator Performance to 39 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks
• I/O Drive to 10 mA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 1.0-micron CMOS Technology
• Design Library with over 500 Macro Functions
• Single-Module Sequential Functions
• Wide-Input Combinatorial Functions
• Up to 1232 Programmable Logic Modules
• Up to 998 Flip-Flops
Pr od uc t F am i l y P r o f i l e
Device
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Logic Modules
S-Modules
C-Modules
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
User I/Os (maximum)
Packages
1
A1225A
2,500
6,250
63
25
451
231
220
382
36
15
250,000
83
100 CPGA
100 PQFP
100 VQFP
84 PLCC
A1240A
4,000
10,000
100
40
684
348
336
568
36
15
400,000
104
132 CPGA
144 PQFP
176 TQFP
84 PLCC
A1280A
8,000
20,000
200
80
1,232
624
608
998
36
15
750,000
140
176 CPGA
160 PQFP
176 TQFP
84 PLCC
172 CQFP
85 MHz
67 MHz
36 MHz
Performance
2
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
105 MHz
70 MHz
39 MHz
100 MHz
69 MHz
38 MHz
Notes:
1. See the
“Product Plan” on page 3
for package availability.
2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,
dated 3-28-93, any analysis is not endorsed by PREP.
D e ce m b e r 2 0 0 0
1
© 2000 Actel Corporation
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