above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
t
S
PORT 1
DATA IN
PORT 2
INPUT CLK
(PLL ENABLED)
1 CLOCK @ PLLLOCK
(PLL DISABLED)
I
OUTA
OR I
OUTB
t
H
ORDERING GUIDE
DATA X
Model
DATA Y
Temperature
Range
Package
Description
Package
Option
AD9751AST –40°C to +85°C 48-Lead LQFP ST-48
AD9751-EB
Evaluation Board
NOTE
Min CLK freq only applies when using internal PLL. When PLL is disabled, there
is no minimum CLK frequency.
DATA Y
t
LPW
t
PD
DATA X
t
PD
THERMAL CHARACTERISTIC
Thermal Resistance
Figure 1. I/O Timing
48-Lead LQFP
θ
JA
= 91°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9751 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD9751
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2
3
4, 22
5, 21
6
7–16
17–20, 33–36
23–32
37, 38
39
40
41
42
43
44
45
46
47
48
Mnemonic
RESET
CLK+
CLK–
DCOM
DVDD
PLLLOCK
P1B9–P1B0
RESERVED
P2B9–P2B0
DIV0, DIV1
REFIO
FSADJ
AVDD
I
OUTB
I
OUTA
ACOM
CLKCOM
LPF
PLLVDD
CLKVDD
Description
Internal Clock Divider Reset
Differential Clock Input
Differential Clock Input
Digital Common
Digital Supply Voltage
PLL Lock Indicator Output
Data Bits P1B9 to P1B0, Port 1
Data Bits P2B9 to P2B0, Port 2
Control inputs for PLL and input port selector mode, see Tables I and II for details.
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Embedded System
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