Revision 8
IGLOOe Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low-Power Active FPGA Operation
Flash*Freeze
Technology
Enables
Ultra-Low
Power
Consumption while Maintaining FPGA Content
• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-
Power Flash*Freeze Mode
®
High Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
• Bank-Selectable I/O Voltages—Up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay
• Schmitt Trigger Option on Single-Ended Inputs
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO
®
e Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, Each with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Pro (Professional) I/O
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.2
V,
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
ARM Processor Support in IGLOOe FPGAs
• M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available
with or without Debug
Table 1 • IGLOOe Product Family
IGLOOe Devices
ARM-Enabled IGLOOe Devices
System Gates
VersaTiles (D-flip-flops)
Quiescent Current (typical) in Flash*Freeze Mode (µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits (1,024 bits)
Secure (AES) ISP
CCCs with Integrated PLLs
VersaNet Globals
1
I/O Banks
Maximum User I/Os
Package Pins
FBGA
600,000
13,824
49
108
24
1
Yes
6
18
8
270
FG256, FG484
AGLE600
AGLE3000
M1AGLE3000
3,000,000
75,264
137
504
112
1
Yes
6
18
8
620
FG484, FG896
Notes:
1. Refer to the
Cortex-M1 Handbook
for more information.
2. Six chip (main) and twelve quadrant global networks are available.
3. For devices supporting lower densities, refer to the
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
datasheet.
November 2009
© 2010 Actel Corporation
I
IGLOOe Low Power Flash FPGAs
I/Os Per Package
1
IGLOOe Devices
ARM-Enabled IGLOOe Devices
I/O Types
Package
FG256
FG484
FG896
Single-Ended
I/O
1
165
270
–
Differential
I/O Pairs
79
135
–
Single-Ended
I/O
1
–
341
620
Differential
I/O Pairs
–
168
310
AGLE600
AGLE3000
M1AGLE3000
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the
IGLOOe FPGA Fabric User’s Guide
to
ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For AGLE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (V
REF
) per minibank
(group of I/Os).
6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended
user I/Os available is reduced by one.
7. "G" indicates RoHS-compliant packages. Refer to
"IGLOOe Ordering Information" on page III
for the location of the "G" in the
part number.
IGLOOe FPGAs Package Sizes Dimensions
Package
Length × Width (mm × mm)
Nominal Area (mm2)
Pitch (mm)
Height (mm)
FG256
17 × 17
289
1
1.6
FG484
23 × 23
529
1
2.23
FG896
31 × 31
961
1
2.23
IGLOOe Device Status
IGLOOe Devices
AGLE600
AGLE3000
Status
Production
Production
M1AGLE3000
Production
M1 IGLOOe Devices
Status
II
R ev i si o n 8
IGLOOe Low Power Flash FPGAs
IGLOOe Ordering Information
AGLE3000
V2
_
FG
G
896
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Package Lead Count
Lead-Free Packaging
Blank = St andard Packaging
G = RoHS-Compliant Packaging
Package Type
FG = Fine Pit ch Ball Grid Array (1.0 mm pit ch)
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOOe Devices
AGLE600 = 600,000 Syst em Gat es
AGLE3000 = 3,000,000 System Gates
IGLOOe Devices with Cortex-M1
M1AGLE3000 = 3,000,000 System Gates
Note:
Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
R e visi on 8
III
IGLOOe Low Power Flash FPGAs
Temperature Grade Offerings
AGLE600
Package
FG256
FG484
FG896
C, I
C, I
–
AGLE3000
M1AGLPE3000
–
C, I
C, I
Note:
C = Commercial temperature range: 0°C to 70°C ambient temperature.
I = Industrial temperature range: –40°C to 85°C ambient temperature.
References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1
(Cortex-M1).
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
IV
R ev i si o n 8
IGLOOe Low Power Flash FPGAs
Table of Contents
IGLOOe Low-Power Flash FPGAs
IGLOOe Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IGLOOe DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108
Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-109
Package Pin Assignments
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Revision 8
V
PCB Design
京公网安备 11010802033920号
EEWORLD
