PMN23UN
µTrenchMOS™
ultra low level FET
M3D302
Rev. 01 — 16 June 2004
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
1.2 Features
s
TrenchMOS™ technology
s
Very fast switching
s
Low threshold voltage
s
Surface mounted package.
1.3 Applications
s
Battery powered motor control
s
High-speed switch in set top box
power supplies
s
Load switch in notebook computers
s
Driver FET in DC-to-DC converters.
1.4 Quick reference data
s
V
DS
≤
20 V
s
P
tot
≤
1.75 W
s
I
D
≤
6.3 A
s
R
DSon
≤
28 mΩ.
2. Pinning information
Table 1:
Pin
1,2,5,6
3
4
Pinning - SOT457 (TSOP6), simplified outline and symbol
Description
drain (d)
gate (g)
source (s)
6
5
4
Simplified outline
Symbol
d
g
mbb076
1
Top view
2
3
MBK092
s
SOT457 (TSOP6)
Philips Semiconductors
PMN23UN
µTrenchMOS™
ultra low level FET
3. Ordering information
Table 2:
Ordering information
Package
Name
PMN23UN
TSOP6
Description
Plastic surface mounted package; 6 leads
Version
SOT457
Type number
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
sp
= 25
°C
T
sp
= 25
°C;
V
GS
= 4.5 V;
Figure 2
and
3
T
sp
= 70
°C;
V
GS
= 4.5 V;
Figure 2
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
Min
-
-
-
-
-
-
−55
−55
-
Max
20
±8
6.3
5
25.2
1.75
+150
+150
1.45
Unit
V
V
A
A
A
W
°C
°C
A
Source-drain diode
9397 750 13351
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 16 June 2004
2 of 12
Philips Semiconductors
PMN23UN
µTrenchMOS™
ultra low level FET
120
P
der
(%)
80
03aa17
120
I
der
(%)
80
03aa25
40
40
0
0
50
100
150
T
sp
(
°
C)
200
0
0
50
100
150
T
sp
(
°
C)
200
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
102
ID
(A)
03am40
Limit RDSon = VDS / ID
tp = 10
µ
s
100
µ
s
10
1 ms
10 ms
1
DC
100 ms
10-1
10-1
1
10
VDS (V)
102
T
sp
= 25
°C;
I
DM
is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 13351
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 16 June 2004
3 of 12
Philips Semiconductors
PMN23UN
µTrenchMOS™
ultra low level FET
5. Thermal characteristics
Table 4:
R
th(j-sp)
Thermal characteristics
Conditions
Min Typ Max Unit
-
-
70
K/W
thermal resistance from junction to solder point
Figure 4
Symbol Parameter
5.1 Transient thermal impedance
102
Zth(j-sp)
(K/W)
03aj56
δ
= 0.5
0.2
10
0.1
0.05
0.02
1
P
single pulse
tp
T
10-1
10-4
10-3
10-2
10-1
1
10
δ
=
tp
T
t
tp (s)
102
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 13351
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 16 June 2004
4 of 12
Philips Semiconductors
PMN23UN
µTrenchMOS™
ultra low level FET
6. Characteristics
Table 5:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
I
DSS
gate-source threshold voltage
drain-source leakage current
I
D
= 250
µA;
V
GS
= 0 V
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
and
10
V
DS
= 16 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 55
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±8
V; V
DS
= 0 V
V
GS
= 4.5 V; I
D
= 2 A;
Figure 7
and
8
V
GS
= 2.5 V; I
D
= 2 A;
Figure 7
and
8
V
GS
= 1.8 V; I
D
= 1.5 A;
Figure 7
and
8
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 1.7 A; V
GS
= 0 V;
Figure 12
V
DD
= 10 V; R
L
= 10
Ω;
V
GS
= 4.5 V; R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 10 V; f = 1 MHz;
Figure 11
V
DD
= 10 V; V
GS
= 4.5 V; I
D
= 3.8 A;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
10.6
1.8
2.1
740
185
125
8.5
14.5
55
16
0.8
-
-
-
-
-
-
-
-
-
-
1.2
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
-
-
-
-
-
-
0.01
-
10
23
29
37
1.0
10
100
28
34.4
52
µA
µA
nA
mΩ
mΩ
mΩ
20
0.4
-
0.7
-
-
V
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
9397 750 13351
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 16 June 2004
5 of 12
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