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CY28551

Description
universal clock generator for intel, via, and sis®
CategoryPassive components   
File Size1MB,29 Pages
ManufacturerSilicon
Download Datasheet View All

CY28551 Overview

universal clock generator for intel, via, and sis®

CY28551
Universal Clock Generator for Intel, VIA, and SIS
®
Features
• Compliant to Intel
®
CK505
• Selectable CPU clock buffer type for Intel P4 or K8
selection
• Selectable CPU frequencies
• Universal clock to support Intel, SiS and VIA platform
• 0.7V Differential CPU clock for Intel CPU
• 3.3V Differential CPU clock for AMD K8
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 133 MHz Link clock
• 48 MHz USB clock
• 33 MHz PCI clocks
• Dynamic Frequency Control
• Dial-A-Frequency
®
• WatchDog Timer
• Two Independent Overclocking PLLs
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
64-pin QFN package
CPU
x2
SRC
x8
SATA
x1
PCI
x7
REF
x3
LINK
x2
DOT96
x1
24_48M
x1
48M
x1
Block Diagram
VDD_REF
Xin
Xout
Pin Configuration
REF[2:0]
VDD_CPU
CPUT[1:0]
CPUC[1:0]
VDD_PCIEX
PCIET [8:1]
PCIEC[8:1]
VDD_SATA
PCI1/CLKREQ#A
PCI0/CLKREQ#B
**DOC1
PCI4/*SELP4_K8
REF1 /**FSC
PCI5/*SEL0
PCI2/**FSA
PLL Reference
REF2/**MODE
14.318M
Hz
Crystal
RESET_I#/ SRESET#
REF0/ **FSD
PC3/*FSB
VSSREF
VDDPCI
VSSPCI
PLL1
CPU
DOC[2:1]
FS[D:A]
SEL_P4_K8
Divider
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PCI6_F 1
VDD48 2
**SEL24_48 / 24_48M 3
**SEL1/48M 4
VSS48 5
VDDDOT 6
LINK0/DOT96T/SATAT 7
LINK1/DOT96C/SATAC 8
VSSDOT 9
VDDSATA 10
SATAT/PCIEXT0 11
SATAC/PCIEXC0 12
VSSSATA 13
PCIEXT1 14
PCIEXC1 15
VSSPCIE 16
VSSPCIE
VDDPCIE
PCIEXC2
PCIEXC3
PCIEXT2
PCIEXT3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSSPCIE
PCIEXC6
PCIEXC7
PCIEXT5
PCIEXT6
PCIEXT7
VDDREF
SCLK
SDATA
VTTPWRG#/PD
CPUT0
CPUC0
VDDCPU
CPUT1
CPUC1
VSSCPU
**DOC2
VSSA
VDDA
PCIEXT8/CPU_STP#
PCIEXC8/PCI_STP#
VDDPCIE
PCIET0 /SATAT
PCIEC0 /SATAC
PLL2
PCIEX
Divider
M
ultiplexer
Controller
SEL[1:0]
VDD_DO
T
DO
T96T/SATAT/LINK0
DO
T96C/SATAC/LINK1
CY28551
PLL3
SATA
Divider
VDD_PCI
PCI[6:0]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDPCIE
PCIEXC4
PCIEXC5
PCIEXT4
PLL4
Fixed
TPW
R_GD#/PD
SEL24_48
RESET_I#
SDATA
SCLK
Divider
VDD_48
48M
24_48M
I2C
Logic
* Indicates internal pull up
** indicates internal pull down
W
DT
SRESET#
....................... Document #: 001-05675 Rev. D Page 1 of 28
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
XOUT
XIN
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