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W3J512M40KT-1066BC

Description
DDR DRAM, 512MX32, CMOS, PBGA136, BGA-136
Categorystorage    storage   
File Size2MB,43 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

W3J512M40KT-1066BC Overview

DDR DRAM, 512MX32, CMOS, PBGA136, BGA-136

W3J512M40KT-1066BC Parametric

Parameter NameAttribute value
Objectid8062536696
package instructionFBGA,
Reach Compliance Codecompliant
ECCN codeEAR99
access modeSINGLE BANK PAGE BURST
Other featuresAUTO/SELF REFRESH; LG-MAX; WD-MAX; SEATED HT-CALCULATED
JESD-30 codeR-PBGA-B136
length14.6 mm
memory density17179869184 bit
Memory IC TypeDDR DRAM
memory width32
Number of functions1
Number of ports1
Number of terminals136
word count536870912 words
character code512000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512MX32
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
Maximum seat height3.75 mm
self refreshYES
Maximum supply voltage (Vsup)1.45 V
Minimum supply voltage (Vsup)1.283 V
Nominal supply voltage (Vsup)1.35 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
width10.1 mm
W3J512M32K-XBX
W3J512M32KT-XB2X
W3J512M40K(T)-XB3X
*PRELIMINARY
2GB – 512M x 32/40 DDR3 SDRAM 1.35V – 136/204 PBGA Multi-Chip
Package
FEATURES

DDR3 Data Rate = 800, 1,066, 1333 Mb/s

Packages:
• 136 PBGA, 204 PBGA 10 x 14.5mm
• 0.8mm pitch

Supply Voltage = 1.35V

Center terminated push/pull I/O

Differential bidirectional data strobe

Differential clock inputs (CK, CK#)

8n-bit prefetch architecture

Eight internal banks

Fixed Burst length (BL) of 8 and Burst Chop (BC) of 4

Selectable BC4 or BL8 on-the-fly (OTF)

Auto Refresh and Self Refresh Modes

Nominal and dynamic On Die Termination (ODT)

Programmable CAS read latency (CL)

Posted CAS additive latency

Write leveling

Programmable CAS write latency (CWL) based on t
CK

Commercial, industrial and military** temperature ranges

Organized as 1 rank of 512M x 32 or 512M x40

1.5V option available in same packages.
Refer to W3J512M32/40G data sheet.

W3J512M32K-XBX is footprint compatible with Micron
®
M41K256M32 device.
Smart
Fusion2
* This product is under development, is not qualified or characterized and is subject to change or
cancellation without notice.
** Contact factory for availability.
BENEFITS

74% Space savings vs. FBGA

Reduced part count

48% I/O reduction vs. FBGA

Optional:
• Address/control terminations

Differential clock terminations (not populated in XBX
package)

Output drive calibration resistors (RZQ)

Reduced trace lengths for lower parasitic capacitance

Suitable for hi-reliability applications

Enhanced thermal management
TYPICAL APPLICATION
RAM
DDR3
W3J512M32K-XBX
Host
FPGA/
Processor
SSD (SLC)
MSM32/MSM64 (SATA BGA)
W7N16GVHxxBI (PATA BGA)
in)
)
MSD1TB / 512 / 256 / 128 (SATA, 2.5in)
Micron
©
is a registered trademark of Micron Technology, Inc.
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
9
10.5
78
FBGA
2.0
W3J512M40KT-XB3X
2.0
9
78
FBGA
2.0
9
78
FBGA
2.0
9
78
FBGA
9
78
FBGA
W3J512M40KT-XB2X
14.5
10
S
A
V
I
N
G
S
74%***
48%
Area
I/O Count
556.5 mm
2
5 x 78 balls = 390 balls
145 mm
2
204 Balls
*** not including terminations
Microsemi Corporation reserves the right to change products or specifications without notice.
September 2014
Rev. 2
© 2014 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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