W3J512M32K-XBX
W3J512M32KT-XB2X
W3J512M40K(T)-XB3X
*PRELIMINARY
2GB – 512M x 32/40 DDR3 SDRAM 1.35V – 136/204 PBGA Multi-Chip
Package
FEATURES
DDR3 Data Rate = 800, 1,066, 1333 Mb/s
Packages:
• 136 PBGA, 204 PBGA 10 x 14.5mm
• 0.8mm pitch
Supply Voltage = 1.35V
Center terminated push/pull I/O
Differential bidirectional data strobe
Differential clock inputs (CK, CK#)
8n-bit prefetch architecture
Eight internal banks
Fixed Burst length (BL) of 8 and Burst Chop (BC) of 4
Selectable BC4 or BL8 on-the-fly (OTF)
Auto Refresh and Self Refresh Modes
Nominal and dynamic On Die Termination (ODT)
Programmable CAS read latency (CL)
Posted CAS additive latency
Write leveling
Programmable CAS write latency (CWL) based on t
CK
Commercial, industrial and military** temperature ranges
Organized as 1 rank of 512M x 32 or 512M x40
1.5V option available in same packages.
Refer to W3J512M32/40G data sheet.
W3J512M32K-XBX is footprint compatible with Micron
®
M41K256M32 device.
Smart
Fusion2
* This product is under development, is not qualified or characterized and is subject to change or
cancellation without notice.
** Contact factory for availability.
BENEFITS
74% Space savings vs. FBGA
Reduced part count
48% I/O reduction vs. FBGA
Optional:
• Address/control terminations
Differential clock terminations (not populated in XBX
package)
Output drive calibration resistors (RZQ)
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Enhanced thermal management
TYPICAL APPLICATION
RAM
DDR3
W3J512M32K-XBX
Host
FPGA/
Processor
SSD (SLC)
MSM32/MSM64 (SATA BGA)
W7N16GVHxxBI (PATA BGA)
in)
)
MSD1TB / 512 / 256 / 128 (SATA, 2.5in)
Micron
©
is a registered trademark of Micron Technology, Inc.
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
9
10.5
78
FBGA
2.0
W3J512M40KT-XB3X
2.0
9
78
FBGA
2.0
9
78
FBGA
2.0
9
78
FBGA
9
78
FBGA
W3J512M40KT-XB2X
14.5
10
S
A
V
I
N
G
S
74%***
48%
Area
I/O Count
556.5 mm
2
5 x 78 balls = 390 balls
145 mm
2
204 Balls
*** not including terminations
Microsemi Corporation reserves the right to change products or specifications without notice.
September 2014
Rev. 2
© 2014 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
W3J512M40K(T)-XB3X
PRELIMINARY
FIGURE 2B – FUNCTIONAL BLOCK DIAGRAM FOR W3J512M32KT-XB2X
A0-15, BA0-2, RAS#, CAS#
WE#, RST#, CKE, ODT, CS#
CK#
CK
26
CK# CK
512M x 8
IC1
DM
DQ
DQS
11
DQS0, DQS0#
DM0, DQ0-7
ZQ
240Ω
26
CK# CK
512M x 8
IC2
DM
DQ
DQS
11
DQS1, DQS1#
DM1, DQ8-15
ZQ
240Ω
26
CK# CK
512M x 8
IC3
DM
DQ
DQS
11
DQS2, DQS2#
DM2, DQ16-23
ZQ
240Ω
26
CK# CK
512M x 8
IC4
DM
DQ
DQS
11
DQS3, DQS3#
DM3, DQ24-31
ZQ
240Ω
V
TT
NOTES:
• Block diagram shows actual
fl
y-by order.
• Calibration resistors (RZQ) are included.
• Clock termination is included.
• Address/Control terminations are included.
R
TT
R
TT
25
Microsemi Corporation reserves the right to change products or specifications without notice.
September 2014
Rev. 2
© 2014 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
W3J512M40K(T)-XB3X
PRELIMINARY
FIGURE 2D – FUNCTIONAL BLOCK DIAGRAM FOR W3J512M40K(T)-XB3X
A0-15, BA0-2, RAS#, CAS#
WE#, RST#, CKE, ODT, CS#
CK#
CK
26
CK# CK
CK# CK
26
512M x 8
IC1
DM
DQ
DQS
11
DQS0, DQS0#
DM0, DQ0-7
DM
512M x 8
DQ
DQS
IC4
11
DQS3, DQS3#
DM3, DQ24-31
ZQ
240Ω
ZQ
240Ω
26
CK# CK
CK# CK
26
512M x 8
IC2
DM
DQ
DQS
11
DQS1, DQS1#
DM1, DQ8-15
512M x 8
DQ
IC5
DQS
DM
11
DQS4, DQS4#
DM4, DQ32-39
ZQ
240Ω
ZQ
240Ω
V
TT
26
CK# CK
R
TT
R
TT
25
**
512M x 8
IC3
DM
DQ
DQS
11
DQS2, DQS2#
DM2, DQ16-23
ZQ
240Ω
NOTES:
• Block diagram shows actual
fl
y-by order.
• Calibration resistors (RZQ) are included.
• Clock termination is included.
** Address/Control terminations are optional.
Microsemi Corporation reserves the right to change products or specifications without notice.
September 2014
Rev. 2
© 2014 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp