MC7457VG733NC datasheet, PDF - EEWORLD Datasheet

Freescale Semiconductor

Data Sheet: Technical Data

MPC7457EC

Rev. 8, 04/2013

MPC7457

RISC

Microprocessor

This hardware specification is primarily concerned

with the MPC7457; however, unless otherwise

noted, all information here also applies to the

MPC7447. The MPC7457 and MPC7447 are

implementations of the PowerPC™ microprocessor

family of reduced instruction set computer (RISC)

microprocessors. This hardware specification

describes pertinent electrical and physical

characteristics of the MPC7457. For functional

characteristics of the processor, refer to the

MPC7450 RISC Microprocessor Family User’s

Manual.

To locate any published updates for this hardware

specification, refer to the website listed on the back

page of this document.

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Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Comparison with the MPC7455, MPC7445,

MPC7450, MPC7451, and MPC7441 . . . . . . . . . . . . 9

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electrical and Thermal Characteristics . . . . . . . . . . . 11

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 44

System Design Information . . . . . . . . . . . . . . . . . . . 50

Document Revision History . . . . . . . . . . . . . . . . . . . 68

Part Numbering and Marking . . . . . . . . . . . . . . . . . . 65

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

Overview

1

Overview

The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors from Freescale.

The MPC7457 implements the full PowerPC 32-bit architecture and is targeted at networking and

computing systems applications. The MPC7457 consists of a processor core, a 512-Kbyte L2, and an

internal L3 tag and controller that support a glueless backside L3 cache through a dedicated

high-bandwidth interface. The MPC7447 is identical to the MPC7457 except that it does not support the

L3 cache interface.

Figure 1

shows a block diagram of the MPC7457. The core is a high-performance superscalar design

supporting a double-precision floating-point unit and a SIMD multimedia unit.

The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to

main memory and other system resources. The L3 interface supports 1, 2, or 4 Mbytes of external SRAM

for L3 cache and/or private memory data. For systems implementing 4 Mbytes of SRAM, a maximum of

2 Mbytes may be used as cache; the remaining 2 Mbytes must be private memory.

Note that the MPC7457 is a footprint-compatible, drop-in replacement in a MPC7455 application if the

core power supply is 1.3 V.

2

Features

This section summarizes features of the MPC7457 implementation of the PowerPC architecture.

Major features of the MPC7457 are as follows:

• High-performance, superscalar microprocessor

— As many as four instructions can be fetched from the instruction cache at a time.

— As many as three instructions can be dispatched to the issue queues at a time.

— As many as 12 instructions can be in the instruction queue (IQ).

— As many as 16 instructions can be at some stage of execution simultaneously.

— Single-cycle execution for most instructions

— One instruction per clock cycle throughput for most instructions

— Seven-stage pipeline control

• Eleven independent execution units and three register files

— Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target

instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can

be made available from the instruction cache. Typically, a fetch that hits the BTIC provides

the first four instructions in the target stream.

– 2048-entry branch history (BHT) with 2 bits per entry for 4 levels of prediction—not-taken,

strongly not-taken, taken, and strongly taken

– Up to three outstanding speculative branches

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

2

Freescale Semiconductor

Features

– Branch instructions that do not update the count register (CTR) or link register (LR) are

often removed from the instruction stream.

– Eight-entry link register stack to predict the target address of Branch Conditional to Link

Register (bclr) instructions

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

3

4

Instruction Unit

Branch Processing Unit

Fetcher

Tags

LR

BTIC (128-Entry)

CTR

Instruction Queue

(12-Word)

SRs

(Shadow)

128-Entry

ITLB

Instruction MMU

128-Bit (4 Instructions)

32-Kbyte

I Cache

96-Bit (3 Instructions)

32-Kbyte

D Cache

Reservation

Stations (2-Entry)

EA

Completes up

to three

instructions

per clock

VR File

16 Rename

Buffers

Integer

Unit 2

Integer

Unit 122

Unit

(3)

+++

32-Bit

x÷

Vector

FPU

32-Bit

128-Bit

16 Rename

Buffers

Reservation

Stations (2)

GPR File

Reservation

Station

Vector

Touch

Queue

Load/Store Unit

Vector Touch Engine

+ (EA Calculation)

Finished

Stores

L1 Castout

PA

FPR File

16 Rename

Buffers

Reservation

Stations (2)

Floating-

Point Unit

L1 Push

Completed

Stores

+ x÷

FPSCR

Load Miss

64-Bit

Vector

Integer

Unit 1

L1 Service

Queues

Features

Additional Features

• Time Base Counter/Decrementer

• Clock Multiplier

• JTAG/COP Interface

• Thermal/Power Management

• Performance Monitor

Completion Unit

Completion Queue

(16-Entry)

Reservation Reservation Reservation Reservation

Station

Figure 1. MPC7457 Block Diagram

512-Kbyte Unified L2 Cache Controller

Line

Block 0 (32-Byte)

Block 1 (32-Byte)

Tags Status

Status

L3 Cache Controller

1

Line Block 0/1

Tags Status

L3CR

L2 Prefetch (3)

Bus Accumulator

L2 Store Queue (L2SQ)

Snoop Push/

L1 Castouts

Interventions

(4)

Vector

Permute

Unit

Vector

Integer

Unit 2

Memory Subsystem

System Bus Interface

Load

Queue (11)

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

19-Bit Address

64-Bit Data

(8-Bit Parity)

External SRAM

(1, 2, or 4 Mbytes)

L1 Store Queue

(LSQ)

L1 Load Queue (LLQ)

L1 Load Miss (5)

Bus Store Queue

Castout

Queue (9)/

Push

Queue (10)

2

Bus Accumulator

Instruction Fetch (2)

Cacheable Store Request(1)

Freescale Semiconductor

Notes:

1. The L3 cache interface is not implemented on the MPC7447.

2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries.

The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.

36-Bit

Address Bus

64-Bit

Data Bus

Features

•

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions

– IU2 executes miscellaneous instructions including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions

— Five-stage FPU and a 32-entry FPR file

– Fully IEEE 754-1985 compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Four vector units and 32-entry vector register file (VRs)

– Vector permute unit (VPU)

– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as

vector add instructions (for example,

vaddsbs, vaddshs,

and

vaddsws)

– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as

vector multiply add instructions (for example,

vmhaddshs, vmhraddshs,

and

vmladduhm)

– Vector floating-point unit (VFPU)

— Three-stage load/store unit (LSU)

– Supports integer, floating-point, and vector instruction load/store traffic

– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream

operations

– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle

throughput

– Four-cycle FPR load latency (single, double) with one-cycle throughput

– No additional delay for misaligned access within double-word boundary

– Dedicated adder calculates effective addresses (EAs)

– Supports store gathering

– Performs alignment, normalization, and precision conversion for floating-point data

– Executes cache control and TLB instructions

– Performs alignment, zero padding, and sign extension for integer data

– Supports hits under misses (multiple outstanding misses)

– Supports both big- and little-endian modes, including misaligned little-endian accesses

Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,

respectively, in a cycle. Instruction dispatch requires the following:

— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2

— A maximum of three instructions can be dispatched to the issue queues per clock cycle

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

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