MT88E45BSR1 datasheet, PDF - EEWORLD Datasheet

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MT88E45BSR1: DescriptionIC cnic cidCW cid 20soic; CategoryWireless rf/communication Telecom circuit; File Size991KB，30 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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IC cnic cidCW cid 20soic

MT88E45BSR1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
Parts packaging code	SOIC
package instruction	SOP,
Contacts	20
Reach Compliance Code	compliant
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	12.8 mm
Number of functions	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Maximum seat height	2.65 mm
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	TELEPHONE CALLING NO IDENTIFICATION CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.4 mm

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MT88E45

4-Wire Calling Number Identification

Circuit 2 (4-Wire CNIC2)

Data Sheet

Features

•

Compatible with:

•

Bellcore GR-30-CORE, SR-TSV-002476,

ANSI/TIA/EIA-716, TIA/EIA-777;

ETSI ETS 300 778-1 (FSK only variant) & -2;

BT (British Telecom) SIN227 & SIN242

MT88E45BN

MT88E45BS

MT88E45BSR

MT88E45BNR

MT88E45BN1

MT88E45BNR1

MT88E45BS1

MT88E45BSR1

Ordering Information

Tubes

Tape & Reel

Tubes

Tape & Reel,

Bake & Drypack

20 Pin SOIC*

Tubes, Bake & Drypack

20 Pin SOIC*

Tubes, Bake & Drypack

*Pb Free Matte Tin

-40°C to +85°C

SSOP

SOIC

SSOP

SSOP*

June 2006

Bellcore ‘CPE Alerting Signal’ (CAS), ETSI ‘Dual

Tone Alerting Signal’ (DT-AS), BT Idle State and

Loop State ‘Tone Alert Signal’ detection

1200 baud Bell 202 and CCITT V.23 FSK

demodulation

Separate differential input amplifiers with

adjustable gain for Tip/Ring and telephone hybrid

or speech IC connections

Selectable 3-wire FSK data interface (bit stream

or 1 byte buffer)

Facility to monitor the stop bit for framing error

check

FSK Carrier detect status output

3 to 5V +/- 10% supply voltage

Uses 3.579545 MHz crystal or ceramic resonator

Low power CMOS with power down

•

Applications

•

Bellcore CID (Calling Identity Delivery) and

CIDCW (Calling Identity Delivery on Call Waiting)

telephones and adjuncts

ETSI, BT CLIP (Calling Line Identity Presentation)

and CLIP with Call Waiting telephones and

adjuncts

Fax and answering machines

Computer Telephony Integration (CTI) systems

•

FSKen+Tip/Ring CASen

IN1+

IN1-

GS1

IN2+

IN2-

GS2

REF

Bias

Generator

PWDN

Oscillator

Hybrid CASen

MODE

FSKen

PWDN

CASen

MODE

FSK

Bandpass

FSKen

CASen

2130Hz

Bandpass

2750Hz

Bandpass

Mux

Carrier

Detector

STD

Tone

Detection

Algorithm

Guard

Time

FSK

Demodulator

Data Timing

Recovery

DATA

DCLK

DR/STD

PWDN

Anti-Alias

Filter

PWDN

ST/GT

EST

Vdd

Vss

Control Bit

Decode

CASen

CB0 CB1 CB2

OSC1

OSC2

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT88E45

Pin Description

Pin # Name

DATA

Description

Data Sheet

3-wire FSK Interface Data (CMOS Output).

Mark frequency corresponds to logical 1. Space

frequency corresponds to logical 0.

In mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to the DATA pin

directly.

In mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte and the trailing

stop bit are stored in a 9 bit buffer. At the end of each word signalled by the DR/STD pin, the

microcontroller should shift the byte out onto the DATA pin by applying 8 read pulses to the DCLK

pin. A 9th DCLK pulse will shift out the stop bit for framing error checking.

DR/STD

3-wire FSK Interface Data Ready/CAS Detection Delayed Steering (CMOS Output).

Active

low.

When FSK demodulation is enabled via the CB1 and CB2 pins this pin is the Data Ready output.

It denotes the end of a word. In both FSK interface modes 0 and 1, it is normally hi and goes low

for half a bit time at the end of a word. But in mode 1 if DCLK starts during DR low, the first rising

edge of the DCLK input will return DR to high. This feature allows an interrupt requested by a low

going DR to be cleared upon reading the first DATA bit.

When CAS detection is enabled via the CB1 and CB2 pins this pin is the Delayed Steering output.

It goes low to indicate that a time qualified CAS has been detected.

EST

CAS Detection Early Steering (CMOS Output).

Active high. This pin is the raw CAS detection

output. It goes high to indicate the presence of a signal meeting the CAS accept frequencies and

signal level. It is used in conjunction with the ST/GT pin and external components to time qualify

the detection to determine whether the signal is a real CAS.

ST/GT

CAS Detection Steering/Guard Time (CMOS Output/Analog Input).

It is used in conjunction

with the EST pin and external components to time qualify the detection to determine whether the

signal is a real CAS.

A voltage greater than V

TGt

at this pin causes the MT88E45B to indicate that a CAS has been

detected by asserting the DR/STD pin low. A voltage less than V

TGt

frees up the MT88E45B to

accept a new CAS and returns DR/STD to high.

Carrier Detect (CMOS Output).

Active low.

A logic low indicates that an FSK signal is present. A time hysteresis is provided to allow for

momentary signal discontinuity. The demodulated FSK data is ignored by the MT88E45B until

carrier detect has been activated.

Positive power supply.

Control Bit 1 (CMOS Input).

Together with CB2 this pin selects the MT88E45B’s functionality

between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.

When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state

consuming minimal power supply current. See Tables 1 and 2.

Control Bit 2 (CMOS Input).

Together with CB1 this pin selects the MT88E45B’s functionality

between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.

When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state

consuming minimal power supply current. See Tables 1 and 2.

Hybrid Gain Select (Output).

This is the output of the hybrid receive connection op-amp. The op-

amp should be used to connect the MT88E45B to the telephone hybrid or speech IC receive pair.

The hybrid receive signal can be amplified or attenuated at GS2 via selection of the feedback

resistor between GS2 and IN2-. When the CPE is off-hook CAS detection of the GS2 signal

should be enabled via the CB1 and CB2 pins. See Tables 1 and 2.

Hybrid Op-amp Inverting (Input).

Hybrid Op-amp Non-Inverting (Input).

Vdd

CB1

CB2

GS2

IN2-

IN2+

Zarlink Semiconductor Inc.

MT88E45BSR1 Related Products

	MT88E45BSR1	MT88E45BNR1	MT88E45BS1	MT88E45BS	MT88E45BN	MT88E45BSR	MT88E45BNR
Description	IC cnic cidCW cid 20soic	IC cnic cidCW cid 20ssop	IC cnic cidCW cid 20soic	Telephone Circuit, CMOS, PDSO20	Telephone Circuit, CMOS, PDSO20	Telephone Circuit, CMOS, PDSO20	Telephone Circuit, CMOS, PDSO20
Is it Rohs certified?	conform to	conform to	conform to	incompatible	incompatible	incompatible	incompatible
Maker	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi
Parts packaging code	SOIC	SSOP	SOIC	SOIC	SSOP	SOIC	SSOP
Contacts	20	20	20	20	20	20	20
Reach Compliance Code	compliant	compliant	compliant	unknown	unknown	unknown	unknown
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
Number of terminals	20	20	20	20	20	20	20
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SSOP	SOP	SOP	SSOP	SOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm	1.27 mm	0.635 mm	1.27 mm	0.635 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Is it lead-free?	-	Lead free	-	Contains lead	Contains lead	Contains lead	-
Encapsulate equivalent code	-	SSOP20,.3	-	SOP20,.4	SSOP20,.3	SOP20,.4	SSOP20,.3
power supply	-	3/5 V	-	3/5 V	3/5 V	3/5 V	3/5 V
Maximum slew rate	-	8 mA	-	8 mA	8 mA	8 mA	8 mA

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