CX28348 datasheet, PDF - EEWORLD Datasheet

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CX28348: DescriptionDual/Triple/Quad/Hex/Octal-Enhanced DS3/E3 Framer; File Size1MB，195 Pages; ManufacturerETC

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CX28348 Overview

Dual/Triple/Quad/Hex/Octal-Enhanced DS3/E3 Framer

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CX28342/3/4/6/8

Dual/Triple/Quad/Hex/Octal-Enhanced

DS3/E3 Framer

The CX28342/3/4/6/8 provides Dual, Triple, Quad, Hex, and Octal DS3/E3

framers designed to support DS3-M13, DS3-C-bit parity, E3-G.751, and

E3-G.832 transmission formats.

The CX28342/3/4/6/8 provides framing recovery for M13, M23, C-bit

parity, G.751, and G.832 formatted signals. A FIFO buffer in the receive

path can be enabled to reduce jitter on the incoming data. The CX28342/

3/4/6/8 devices allow for ease of configuration, while providing

maximum flexibility to support the transmission and recovery of industry

standard formats. It provides a flexible overhead bit generation method in

DS3/E3 modes to source overhead bits on an individual framer.

Distinguishing Features

NOTE:

The index letter

appearing in a register’s name, represents the

channel number, one per channel.

Functional Block Diagram

VCO

RXCKI

RXPOS

RXNEG

LINECK

TXPOS

TXNEG

TCLKO

RXDAT

RXMSY

RXGAPCK

REXTCK

Channel 1

TXDATI

Framer

TXCKI

(Typical All Channels)

TEXT

TEXTCK

TXSY

TXGAPCK

Two, three, four, six, eight independent T3/

E3 framers in one package

Line coding supported:

T3-B3ZS, NRZ, AMI

E3-HDB3, NRZ, AMI

Framing supported:

T3-M13, M23, C-bit parity

E3-G.751, G.832

Inserts and extracts overhead bits

Full FEAC and TDL channels support

Full Performance Monitoring support per

T1.231

Integrated Dejitter FIFO

Glueless interfaces to the following

processors:

Intel: 8051, 8151, 8031, 8751, 8x251

Motorola: 68000, 68020, 68030, 68302

An asynchronous processor interface

LIU Interfaces:

Glueless interface to Conexant’s DS3/E3

LIU (CX2832/3)

Option for a definition of LIU’s clocks

polarity-sampling edge

Power Supplies and Power Consumption

I/O 3.3 V, input 5 V-tolerant, core 2.5 V

Requires 3.3 V and 2.5 V power

supplies. Optional 5 V supply required

for 5 V input tolerance

Low power operation (<200 mW per

port)

System Side

Line Side

Applications

Channel 2

Framer

ONESEC

MOTO

ALE

DTACK

INTR

Digital Cross-Connect Systems

Digital PCM Switches

Access Concentrators

CSUs

ATM Switches

Concentrators

PBXs

Routers

Test Equipment

Microprocessor

Interface

Channel 3

Framer

Channel 4

Framer

Testing

JTAG boundary scan support

28348-DSH-001-B

Mindspeed Technologies™

February

2003

Contents

Figures

Tables

1.1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1.1

DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.1.2

E3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Pin Descriptions (CX28342/3/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Pin Descriptions (CX28346/8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2

1.3

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1

Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1

Transmitter Overhead Bit Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1.1

DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1.2

E3–G.751 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1.3

E3–G.832 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2

Alarm Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2.1

Loss of Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2.2

DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2.3

E3-G.751 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2.4

E3-G.832 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3

Terminal Data Link Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3.1

HDLC/LAPD Formatting Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3.2

FIFO Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3.3

Initial Setup of Transmit Data Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3.4

Sending Message Using the FIFO—Normal Operation . . . . . . . . . . . . . . . . . . . .

2.1.3.5

FIFO Special Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4

FEAC Channel Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4.1

Single Code-Word Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4.2

Repetitive Code-Word Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5

Test Equipment—Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5.1

DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5.2

E3-G.751 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5.3

E3-G.832 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5.4

Line Coding Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3

2-11

2-12

2-15

2-16

2-18

2-19

2-21

2-22

2-23

2-24

2-25

2-26

2-27

2-29

2-30

2-31

2-32

2-33

28348-DSH-001-B

Mindspeed Technologies™

iii

Contents

CX28342/3/4/6/8 Data Sheet

2.2

2.3

2.4

2.5

Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1

Line-Side Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2

System-Side Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3

Clock Dejitter FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4

Overhead Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4.1

Processing of Overhead Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4.2

Internal Processing of Overhead Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5

Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.1

Bipolar Violation (BPV), Excessive Zeros (EXZ), and Line Code Violation (LCV) .

2.2.5.2

Loss of Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.3

Framing Bit Error (FBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.4

Out of Frame (OOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.5

Severely Errored Frame (SEF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.6

Alarm Indication Signal (AIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.7

Idle Signal (IDLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.8

Parity Error (PER) and P-Bit Disagreement (PBD) . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.9

Path Parity Error (PPER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5.10 Remote Alarm/Defect Indication (RAI/RDI), X-bit disagreement (XBD) . . . . . . .

2.2.5.11 Far-End Block Error/Remote Error Indication (FEBE/REI) . . . . . . . . . . . . . . . . . .

2.2.6

One-Second Counter Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7

Terminal Data Link Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7.1

Initial Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7.2

Writing Messages into the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7.3

Reading Messages from the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.8

Far-End Alarm and Control Channel Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.8.1

Writing into the FEAC Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.8.2

Reading from the FEAC Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1

Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2

Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3

Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4

Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.5

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6

Initialization Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1

Shallow Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.2

Remote Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.3

Payload Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.4

Source Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Joint Test Access Group (JTAG) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1

Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-35

2-36

2-40

2-41

2-42

2-44

2-45

2-46

2-47

2-48

2-49

2-51

2-52

2-53

2-55

2-57

2-58

2-59

2-60

2-62

2-63

2-64

2-65

Mindspeed Technologies™

28348-DSH-001-B

CX28348 Related Products

	CX28348	CX28342	CX28343	CX28344	CX28346
Description	Dual/Triple/Quad/Hex/Octal-Enhanced DS3/E3 Framer	Dual/Triple/Quad/Hex/Octal-Enhanced DS3/E3 Framer	Dual/Triple/Quad/Hex/Octal-Enhanced DS3/E3 Framer	Dual/Triple/Quad/Hex/Octal-Enhanced DS3/E3 Framer	Dual/Triple/Quad/Hex/Octal-Enhanced DS3/E3 Framer

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