CX28342/3/4/6/8
Dual/Triple/Quad/Hex/Octal-Enhanced
DS3/E3 Framer
The CX28342/3/4/6/8 provides Dual, Triple, Quad, Hex, and Octal DS3/E3
framers designed to support DS3-M13, DS3-C-bit parity, E3-G.751, and
E3-G.832 transmission formats.
The CX28342/3/4/6/8 provides framing recovery for M13, M23, C-bit
parity, G.751, and G.832 formatted signals. A FIFO buffer in the receive
path can be enabled to reduce jitter on the incoming data. The CX28342/
3/4/6/8 devices allow for ease of configuration, while providing
maximum flexibility to support the transmission and recovery of industry
standard formats. It provides a flexible overhead bit generation method in
DS3/E3 modes to source overhead bits on an individual framer.
Distinguishing Features
!
!
!
!
!
!
!
!
NOTE:
The index letter
i,
appearing in a register’s name, represents the
channel number, one per channel.
!
Functional Block Diagram
VCO
RXCKI
!
!
RXPOS
RXNEG
LINECK
TXPOS
TXNEG
TCLKO
RXDAT
RXMSY
RXGAPCK
REXTCK
Channel 1
TXDATI
Framer
TXCKI
(Typical All Channels)
TEXT
TEXTCK
TXSY
TXGAPCK
Two, three, four, six, eight independent T3/
E3 framers in one package
Line coding supported:
"
T3-B3ZS, NRZ, AMI
"
E3-HDB3, NRZ, AMI
Framing supported:
"
T3-M13, M23, C-bit parity
"
E3-G.751, G.832
Inserts and extracts overhead bits
Full FEAC and TDL channels support
Full Performance Monitoring support per
T1.231
Integrated Dejitter FIFO
Glueless interfaces to the following
processors:
"
Intel: 8051, 8151, 8031, 8751, 8x251
"
Motorola: 68000, 68020, 68030, 68302
An asynchronous processor interface
LIU Interfaces:
"
Glueless interface to Conexant’s DS3/E3
LIU (CX2832/3)
"
Option for a definition of LIU’s clocks
polarity-sampling edge
Power Supplies and Power Consumption
"
I/O 3.3 V, input 5 V-tolerant, core 2.5 V
"
Requires 3.3 V and 2.5 V power
supplies. Optional 5 V supply required
for 5 V input tolerance
"
Low power operation (<200 mW per
port)
System Side
Line Side
Applications
!
!
Channel 2
Framer
ONESEC
MOTO
AD
A
ALE
RD
WR
CS
DTACK
INTR
!
!
!
!
!
!
!
Digital Cross-Connect Systems
Digital PCM Switches
Access Concentrators
CSUs
ATM Switches
Concentrators
PBXs
Routers
Test Equipment
Microprocessor
Interface
Channel 3
Framer
Channel 4
Framer
Testing
!
JTAG boundary scan support
28348-DSH-001-B
Mindspeed Technologies™
February
2003
Ordering Information
Model Numbe
CX28342
CX28343
CX28344
CX28346
CX28348
Number of Frames
2
3
4
6
8
Package
144 pin ETQFP
144 pin ETQFP
144 pin ETQFP
27 x 27 mm 318-ball PBGA
27 x 27 mm 318-ball PBGA
Ambient Temperature Range
–40 °C to 85 °C
–40 °C to 85 °C
–40 °C to 85 °C
–40 °C to 85 °C
–40 °C to 85 °C
Revision History
Revision
A (Doc # 100542)
A
*
Level
Advance
—
Date
May 2000
September 2001
Created
Added details on memory mapping for CX28346
and CX28348 devices. * Document number
changed from 100542 to 500064A.
Added jitter attenuator information.
Corrected Jitter attenuation information. Rolled up
Errata, document #101317A.
Renumbered document to 28348-DSH-001-A
Revised section 2.2.5.5
Description
B
C
A
B
Preliminary
Release
Release
Release
November 2001
August 2002
December 2002
February 2003
© 2002, 2003
Mindspeed Technologies™, A Conexant Business
All Rights Reserved.
Information in this document is provided in connection with Mindspeed Technologies (“Mindspeed”) products. These materials are provided by
Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or
omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed
makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to its specifications and product descriptions.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Mindspeed’s Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever.
THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE
AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR
OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF
THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE
LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST
REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling
Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from
such improper use or sale.
The following are trademarks of Conexant Systems, Inc.: Mindspeed Technologies™, the Mindspeed™ logo, and “Build It First”™. Product
names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and
names are the property of their respective owners.
For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at
www.mindspeed.com
which is
incorporated by reference.
28348-DSH-001-B
Mindspeed Technologies™
ii
Contents
Contents
Figures
Tables
1.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1
DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.2
E3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Pin Descriptions (CX28342/3/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Pin Descriptions (CX28346/8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2
1.3
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
Transmitter Overhead Bit Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1.1
DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1.2
E3–G.751 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1.3
E3–G.832 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2
Alarm Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2.1
Loss of Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2.2
DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2.3
E3-G.751 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2.4
E3-G.832 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3
Terminal Data Link Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3.1
HDLC/LAPD Formatting Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3.2
FIFO Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3.3
Initial Setup of Transmit Data Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3.4
Sending Message Using the FIFO—Normal Operation . . . . . . . . . . . . . . . . . . . .
2.1.3.5
FIFO Special Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4
FEAC Channel Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4.1
Single Code-Word Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4.2
Repetitive Code-Word Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5
Test Equipment—Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5.1
DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5.2
E3-G.751 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5.3
E3-G.832 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5.4
Line Coding Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
2-11
2-12
2-15
2-16
2-18
2-18
2-19
2-21
2-22
2-23
2-23
2-24
2-25
2-26
2-27
2-29
2-30
2-30
2-31
2-31
2-32
2-33
2-33
28348-DSH-001-B
Mindspeed Technologies™
iii
Contents
CX28342/3/4/6/8 Data Sheet
2.2
2.3
2.4
2.5
Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Line-Side Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
System-Side Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Clock Dejitter FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4
Overhead Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4.1
Processing of Overhead Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4.2
Internal Processing of Overhead Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.1
Bipolar Violation (BPV), Excessive Zeros (EXZ), and Line Code Violation (LCV) .
2.2.5.2
Loss of Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.3
Framing Bit Error (FBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.4
Out of Frame (OOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.5
Severely Errored Frame (SEF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.6
Alarm Indication Signal (AIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.7
Idle Signal (IDLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.8
Parity Error (PER) and P-Bit Disagreement (PBD) . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.9
Path Parity Error (PPER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5.10 Remote Alarm/Defect Indication (RAI/RDI), X-bit disagreement (XBD) . . . . . . .
2.2.5.11 Far-End Block Error/Remote Error Indication (FEBE/REI) . . . . . . . . . . . . . . . . . .
2.2.6
One-Second Counter Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7
Terminal Data Link Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7.1
Initial Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7.2
Writing Messages into the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7.3
Reading Messages from the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8
Far-End Alarm and Control Channel Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8.1
Writing into the FEAC Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8.2
Reading from the FEAC Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4
Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.6
Initialization Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1
Shallow Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2
Remote Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3
Payload Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4
Source Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Joint Test Access Group (JTAG) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-35
2-35
2-36
2-40
2-41
2-41
2-42
2-44
2-45
2-45
2-45
2-46
2-46
2-47
2-47
2-47
2-48
2-48
2-48
2-48
2-49
2-51
2-52
2-53
2-55
2-57
2-57
2-58
2-58
2-58
2-58
2-59
2-59
2-60
2-62
2-62
2-63
2-63
2-64
2-65
2-65
iv
Mindspeed Technologies™
28348-DSH-001-B
CX28342/3/4/6/8 Data Sheet
Contents
3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
3.3
Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
General1 Control Register (GCR00)
3-7
General2 Control Register (GCR01)
3-8
Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Mode Control Register (CR00i)
3-9
Counter Interrupt Control Register (CR01i)
3-10
Dual-Edge Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Alarm Start Interrupt Control Register (CR02i)
3-11
Alarm End Interrupt Control Register (CR03i)
3-12
Feature Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Feature1 Control Register (CR04i)
3-13
Feature2 Control Register (CR05i)
3-14
Feature3 Control Register (CR06i)
3-15
Feature4 Control Register (CR07i)
3-16
Feature5 Control Register (CR08i)
3-17
Transmit Overhead Insertion Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Transmit Overhead Insertion1 Control Register (CR09i)
3-19
DS3-C Bit Parity
3-20
REXTCK Control Register (CR11i)
3-22
Receive Overhead Control Register (CR12i)
3-23
Transmit Data Link Control Register (CR13i)
3-24
Transmit Data Link Threshold Control Register (CR14i)
3-24
Transmit Data Link Message Byte (CR15i)
3-25
Receive Data Link Control Register (CR16i)
3-25
Receive Data Link Threshold Control Register (CR17i)
3-26
Transmit FEAC Channel Byte (CR18i)
3-26
Error Insertion Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
Error Insertion1 Control Register (CR19i)
3-27
Error Insertion2 Control Register (CR20i)
3-28
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Source Channel Status Register (GSR00)
3-29
Part Number/Hardware Version Register (GSR01)
3-30
Channel Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
DS3/E3 Maintenance Status Register (SR00i)
3-31
Interrupt Source Status Register (SR01i)
3-32
Counter Interrupt Status Register (SR02i)
3-33
Dual-Edge Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
Alarm Start Interrupt Status Register (SR03i)
3-34
Alarm End Interrupt Status Register (SR04i)
3-35
E3-832 MA Fields Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
E3-G.832 MA Fields Status Register (SR06i)
3-36
E3-G.832 SSM Field Status Register (SR07i)
3-36
Transmit Data Link FEAC Status Register (SR08i)
3-37
Receive Data Link Status Register (SR11i)
3-38
Receive Data Link Message Byte (SR12i)
3-39
Receive FEAC Status Register (SR17i)
3-41
Receive AIC Byte (SR18i)
3-41
3.4
3.5
28348-DSH-001-B
Mindspeed Technologies™
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