TDA7448
6 CHANNEL VOLUME CONTROLLER
1
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FEATURES
6 CHANNEL INPUTS
6 CHANNEL OUTPUTS
VOLUME ATTENUATION RANGE OF
0 TO -79dB
VOLUME CONTROL IN 1.0dB STEPS
6 CHANNEL INDEPENDENT CONTROL
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
Figure 1. Package
SO-20
Table 1. Order Codes
Part Number
TDA7448
TDA744813TR
Package
SO-20
Tape & Reel
2
DESCRIPTION
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are ob-
tained.
The TDA7448 is a 6 channel volume controller for
quality audio applications in Multi-Channels Audio
Systems
Figure 2. Block Diagram
IN1
2
50K
7
VOLUME
OUT1
IN2
19
50K
14
VOLUME
OUT2
IN3
3
50K
6
VOLUME
OUT3
IN4
18
50K
15
VOLUME
OUT4
IN5
4
50K
5
VOLUME
OUT5
IN6
17
50K
16
VOLUME
10
9
12
1
V
S
OUT6
GND
CREF
11
20
SUPPLY
I
2
C BUS
DECODER
SCL
SDA
ADDR
D02AU1396
June 2004
REV. 3
1/14
TDA7448
Table 2. Absolute Maximum Ratings
Symbol
V
S
T
amb
T
stg
Operating Supply Voltage
Operating Ambient Temperature
Storage Temperature Range
Parameter
Value
10.5
0 to 70
-55 to 150
Unit
V
°C
°C
Figure 3. Pin Connection
(Top view)
V
S
IN1
IN3
IN5
OUT5
OUT3
OUT1
N.C.
SDA
SCL
1
2
3
4
5
6
7
8
9
10
D02AU1397
20
19
18
17
16
15
14
13
12
11
CREF
IN2
IN4
IN6
OUT6
OUT4
OUT2
N.C.
ADDR
GND
Table 3. Thermal Data
Symbol
R
th j-pin
Parameter
thermal Resistance junction-pins
Value
150
Unit
°C/W
Table 4. Quick Reference Data
Symbol
V
S
V
CL
THD
S/N
S
C
Supply Voltage
Max Input Signal Handling
Total Harmonic Distortion V = 1Vrms f =1KHz
Signal to Noise Ratio Vout = 1Vrms
Channel Separation f = 1KHz
Volume Control (1dB step)
Mute Attenuation
-79
90
Parameter
Min.
4.75
2
0.01
100
90
0
0.1
Typ.
9
Max.
10
Unit
V
Vrms
%
dB
dB
dB
dB
2/14
TDA7448
Table 5. Electrical Characteristcs
(refer to the test circuit T
amb
= 25°C, V
S
= 9V, R
L
= 10KΩ, R
G
= 600Ω, unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
S
I
S
SVR
Supply Voltage
Supply Current
Ripple Rejection
4.75
9
7
80
10
V
mA
dB
INPUT STAGE
R
IN
V
CL
S
IN
Input Resistance
Clipping Level
Input Separation
THD = 0.3%
The selected input is grounded
through a 2.2µ capacitor
35
2
50
2.5
90
65
KΩ
Vrms
dB
VOLUME CONTROL
C
RANGE
A
VMAX
A
STEP
E
A
Control Range
Max. Attenuation
Step Resolution
Attenuation Set Error
A
V
= 0 to -24dB
A
V
= -24 to -79dB
E
T
Tracking Error
A
V
= 0 to -24dB
A
V
= -24 to -79dB
V
DC
A
mute
DC Step
Mute Attenuation
adyacent attenuation steps
0.5
-1
-2.0
-1
-2
-3
79
79
1
0
0
0
0
0
90
1.5
1
2.0
1
2
3
dB
dB
dB
dB
dB
dB
dB
mV
db
AUDIO OUTPUTS
V
CLIP
R
L
V
DC
Clipping Level
Output Load Resistance
DC Voltage Level
THD = 0.3%
2
2
4.5
2.5
Vrms
KΩ
V
GENERAL
E
NO
S/N
S
C
THD
Output Noise
Signal to Noise Ratio
Channel Separation left/Right
Distortion
A
V
= 0; V
I
= 1Vrms
BW = 20Hz to 20KHz
All gains = 0dB, Flat
All gains = 0dB; V
O
= 1Vrms
80
10
100
90
0.01
0.1
15
µV
dB
dB
%
BUS INPUT
V
Il
V
IH
I
IN
V
O
Input Low Voltage
Input High Voltage
Input Current
Output Voltage SDA
Achnowledge
V
IN
= 0.4V
I
O
= 1.6mA
2.5
-5
0.4
5
0.8
1
V
V
µA
V
3/14
TDA7448
Figure 4. Test circuit
0.47µF
IN1
IN1
2
50K
0.47µF
IN2
IN2
19
50K
0.47µF
IN3
IN3
3
50K
0.47µF
IN4
IN4
18
50K
0.47µF
IN5
IN5
4
50K
0.47µF
IN6
IN6
17
50K
GND
CREF
10µF
11
20
V
S
SUPPLY
1
I
2
C BUS
DECODER
10
9
11
SCL
SDA
ADDR
16
VOLUME
OUT6
5
VOLUME
OUT5
15
VOLUME
OUT4
6
VOLUME
OUT3
14
VOLUME
OUT2
7
VOLUME
OUT1
D02AU1406
3
APPLICATION SUGGESTIONS
Figure 6. THD vs. R
LOAD
The volume control range is 0 to -79dB, by 1dB step
resolution.
The very high resolution allows the implementation of
systems free from any noise acoustical effect.
3.1 CREF
The suggested 10µF reference capacitor (CREF)
value can be reduced to 4.7µF if the application re-
quires faster power ON.
Figure 5. THD vs. frequency
Figure 7. Channel separation vs. frequency
4/14
TDA7448
4
I
2
C BUS INTERFACE
Data transmission from microprocessor to the TDA7448 and vice versa takes place through the 2 wires I
2
C BUS in-
terface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
4.1 Data Validity
As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig. 9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
4.4 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10). The
peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the
µP
can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 8. Data Validity on the I
2
CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 9. Timing Diagram of I
2
CBUS
SCL
I
2
CBUS
SDA
D99AU1032
START
STOP
Figure 10. Acknowledge on the I
2
CBUS
SCL
1
2
3
7
8
9
SDA
MSB
START
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
5/14
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