Document Revision History
Version History
Rev 1.0
Rev 2.0
Rev 3.0
Description of Change
Pre-Release version, Alpha customers only
Initial Public Release
Corrected typo in
Table 10-4,
Flash Endurance is 10,000 cycles. Addressed additional
grammar issues.
Added “Typical Min” values to
Table 10-16.
Edited grammar, spelling, consistency of
language throughout family. Updated values in Current Consumption per Power Supply Pin,
Table 10-7,
Regulator Parameters,
Table 10-9,
External Clock Operation Timing
Requirements
Table 10-13,
SPI Timing,
Table 10-17,
ADC Parameters,
Table 10-23,
and IO
Loading Coefficients at 10MHz,
Table 10-24.
Added
Part 4.8.
Added the word “access” to FM Error Interrupt in
Table 4-5.
Removed min
and max numbers. Clarified CSBAR 0 and CSBAR 1 reset values in
Table 4-10.
Removed
min and max numbers, only documenting Typ. numbers for LVI in
Table 10-6.
Updated numbers in
Table 10-7
and
Table 10-8
with more recent data. Corrected typo in
Table 10-3
in Pd characteristics.
Replaced any reference to Flash Interface Unit with Flash Memory Module. Added note to
V
CAP
pin in
Table ?-??????.
Removed unneccessary notes in
Table 10-12.
Corrected
temperature range in
Table 10-14.
Added ADC calibration information to
Table 10-23
and
new graphs in
Figure 10-21.
Clarified
Table 10-22.
Corrected Digital Input Current Low (pull-up enabled) numbers in
Table 10-5.
Removed text and Table 10-2. Replaced with note to
Table 10-1.
Added 56F8145 information; edited to indicate differences in 56F8345 and 56F8145.
Reformatted for Freescale look and feel. Updated Temperature Sensor and ADC tables;
updated balance of electrical tables for consistency throughout family. Clarified I/O power
description in
Table ?-??????,
added note to
Table 10-7
and clarified
Section 12.3.
Corrected beginning address for On-Chip Data RAM,
Table 4-6.
Corrected addresses in
Table 4-6.
Corrected
Figure 10-21.
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall life expectancy note, since life expectancy is dependent on
customer usage and must be determined by reliability engineering. Clarified value and unit
measure for Maximum allowed P
D
in
Table 10-3.
Corrected note about average value for
Flash Data Retention in
Table 10-4.
Added new RoHS-compliant orderable part numbers in
Table 13-1.
Updated
Table 10-23
to reflect new value for maximum Uncalibrated Gain Error
Deleted RSTO from Pin Group 2 (listed after
Table 10-1).
Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev 11.0
Rev 12.0
Rev 13.0
Rev 14.0
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8345 Technical Data, Rev. 17
2
Freescale Semiconductor
Preliminary
Document Revision History (Continued)
Version History
Rev 15.0
Description of Change
Updated JTAG ID in
Section 6.5.4.
Added information/corrected state during reset in
Table 2-2.
Clarified external reference crystal frequency for PLL in
Table 10-14
by increasing
maximum value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a
debugging environment, TRST may be tied to V
SS
through a 1K resistor.
Rev 16.0
Rev. 17
Please see http://www.freescale.com for the most current data sheet revision.
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
3
56F8345/56F8145 General Description
Note:
Features in italics are NOT available in the 56F8145 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 128KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Up to two
6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
•
Up to two
Quadrature Decoders
• FlexCAN module
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
RSTO
RESET
6
PWM Outputs
3
4
Current Sense Inputs
or
GPIOC
Fault Inputs
Program Controller
and Hardware
Looping Unit
V
PP
5
JTAG/
EOnCE
Port
V
CAP
4
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
V
DDA
2
V
SSA
2
PWMA
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
6
PWM Outputs
3
4
4
4
5
4
4
Current Sense Inputs
or GPIOD
Fault Inputs
Address
Generation Unit
PWMB
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
AD0
ADCA
AD1
VREF
PAB
PDB
CDBR
CDBW
Memory
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
AD0
ADCB
AD1
TEMP_SENSE
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC
Quad Timer
C or GPIOE
Quad Timer
D or
GPIOE
FlexCAN
System Bus
Control
External Bus
Interface Unit
*
External
Address Bus
Switch
6
5
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
*
External
Data
Bus Switch
4
D7-10 or GPIOF0-3
*
Bus
Control
6
GPIOD0-5 or CS2-7
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
2
Decoding
Peripherals
4
2
Clock
resets
P
System
O
Integration
R
Module
PLL
*
EMI not functional in
this package; use as
GPIO pins
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Interrupt
Watchdog Controller
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA IRQB
CLKO
CLKMODE
56F8345/56F8145 Block Diagram - 128 LQFP
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
5
京公网安备 11010802033920号
EEWORLD
