XCR22LV10-10VO24C datasheet, PDF

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XCR22LV10-10VO24C: Descriptiontotalcmos, universal pld device; CategoryProgrammable logic devices Programmable logic; File Size143KB，14 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XCR22LV10-10VO24C Overview

totalcmos, universal pld device

XCR22LV10-10VO24C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	SOIC
package instruction	TSSOP, TSSOP24,.25
Contacts	24
Reach Compliance Code	unknown
Architecture	PAL-TYPE
maximum clock frequency	125 MHz
JESD-30 code	R-PDSO-G24
JESD-609 code	e0
length	7.8 mm
Humidity sensitivity level	1
Dedicated input times	11
Number of I/O lines	10
Number of entries	22
Output times	10
Number of product terms	132
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
organize	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP24,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Programmable logic type	EE PLD
propagation delay	10 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm

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XCR22LV10: 3V Zero Power,

TotalCMOS, Universal PLD Device

DS047 (v1.1) February 10, 2000

Product Specification

Features

•

Industry's first TotalCMOS™ SPLD - both CMOS

design and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and high speed

- Static current of less than 45

- Dynamic current substantially below that of

competing devices

- Pin-to-pin delay of only 10 ns

True Zero Power device with no turbo bits or power

down schemes

Function/JEDEC map compatible with Bipolar,

UVCMOS, EECMOS 22V10s

Multiple packaging options featuring PCB-friendly

flow-through pinouts (SOL and TSSOP)

- 24-pin TSOIC–uses 93% less in-system space than

a 28-pin PLCC

- 24-pin SOIC

- 28-pin PLCC with standard JEDEC pinout

Available in commercial and industrial operating ranges

Supports mixed voltage systems—5V tolerant I/Os

Advanced 0.5

CMOS process

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Varied product term distribution with up to 16 product

terms per output for complex functions

Programmable output polarity

Synchronous preset/asynchronous reset capability

Security bit prevents unauthorized access

Electronic signature for identification

Design entry and verification using industry standard

CAE tools

Reprogrammable using industry standard device

programmers

Description

The XCR22LV10 is the first SPLD to combine high perfor-

mance with low power, without the need for "turbo bits" or

other power down schemes. To achieve this, Xilinx has

used their FZP design technique, which replaces conven-

tional sense amplifier methods for implementing product

terms (a technique that has been used in PLDs since the

bipolar era) with a cascaded chain of pure CMOS gates.

This results in the combination of low power and high

speed that has previously been unattainable in the PLD

arena. For 5V operation, Xilinx offers the XCR22V10 that

offers high speed and low power in a 5V implementation.

The XCR22LV10 uses the familiar AND/OR logic array

structure, which allows direct implementation of

sum-of-products equations. This device has a programma-

ble AND array which drives a fixed OR array. The OR sum

of products feeds an "Output Macro Cell" (OMC), which can

be individually configured as a dedicated input, a combina-

torial output, or a registered output with internal feedback.

•

Functional Description

The XCR22LV10 implements logic functions as

sum-of-products expressions in a programmable-

AND/fixed-OR logic array. User-defined functions are cre-

ated by programming the connections of input signals into

the array. User-configurable output structures in the form of

I/O macrocells further increase logic flexibility (Figure

1).

DS047 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

XCR22LV10-10VO24C Related Products

	XCR22LV10-10VO24C	XCR22LV10-10PC28I	XCR22LV10-15PC28I	XCR22LV10	XCR22LV10-15VO24C	XCR22LV10-10PC28C	XCR22LV10-15PC28C	XCR22LV10-10VO24I	XCR22LV10-15VO24I
Description	totalcmos, universal pld device	totalcmos, universal pld device	totalcmos, universal pld device	totalcmos, universal pld device	totalcmos, universal pld device	totalcmos, universal pld device	totalcmos, universal pld device	totalcmos, universal pld device	totalcmos, universal pld device
Is it Rohs certified?	incompatible	-	incompatible	-	incompatible	incompatible	incompatible	-	incompatible
Maker	XILINX	-	XILINX	-	XILINX	XILINX	XILINX	-	XILINX
Parts packaging code	SOIC	-	QLCC	-	SOIC	QLCC	QLCC	-	SOIC
package instruction	TSSOP, TSSOP24,.25	-	QCCJ, LDCC28,.5SQ	-	TSSOP, TSSOP24,.25	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ	-	THIN, PLASTIC, SOIC-24
Contacts	24	-	28	-	24	28	28	-	24
Reach Compliance Code	unknown	-	unknown	-	unknown	unknown	unknown	-	unknown
Architecture	PAL-TYPE	-	PAL-TYPE	-	PAL-TYPE	PAL-TYPE	PAL-TYPE	-	PAL-TYPE
maximum clock frequency	125 MHz	-	65 MHz	-	95 MHz	125 MHz	95 MHz	-	65 MHz
JESD-30 code	R-PDSO-G24	-	S-PQCC-J28	-	R-PDSO-G24	S-PQCC-J28	S-PQCC-J28	-	R-PDSO-G24
length	7.8 mm	-	11.5062 mm	-	7.8 mm	11.5062 mm	11.5062 mm	-	7.8 mm
Humidity sensitivity level	1	-	1	-	1	1	1	-	1
Dedicated input times	11	-	11	-	11	11	11	-	11
Number of I/O lines	10	-	10	-	10	10	10	-	10
Number of entries	22	-	22	-	22	22	22	-	22
Output times	10	-	10	-	10	10	10	-	10
Number of product terms	132	-	132	-	132	132	132	-	132
Number of terminals	24	-	28	-	24	28	28	-	24
Maximum operating temperature	70 °C	-	85 °C	-	70 °C	70 °C	70 °C	-	85 °C
organize	11 DEDICATED INPUTS, 10 I/O	-	11 DEDICATED INPUTS, 10 I/O	-	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	-	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL	-	MACROCELL	-	MACROCELL	MACROCELL	MACROCELL	-	MACROCELL
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	TSSOP	-	QCCJ	-	TSSOP	QCCJ	QCCJ	-	TSSOP
Encapsulate equivalent code	TSSOP24,.25	-	LDCC28,.5SQ	-	TSSOP24,.25	LDCC28,.5SQ	LDCC28,.5SQ	-	TSSOP24,.25
Package shape	RECTANGULAR	-	SQUARE	-	RECTANGULAR	SQUARE	SQUARE	-	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	CHIP CARRIER	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER	CHIP CARRIER	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225	-	225	-	225	225	225	-	225
power supply	3.3 V	-	3.3 V	-	3.3 V	3.3 V	3.3 V	-	3.3 V
Programmable logic type	EE PLD	-	EE PLD	-	EE PLD	EE PLD	EE PLD	-	EE PLD
propagation delay	10 ns	-	15 ns	-	15 ns	10 ns	15 ns	-	15 ns
Certification status	Not Qualified	-	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	1.2 mm	-	4.572 mm	-	1.2 mm	4.572 mm	4.572 mm	-	1.2 mm
Maximum supply voltage	3.6 V	-	3.6 V	-	3.6 V	3.6 V	3.6 V	-	3.6 V
Minimum supply voltage	3 V	-	3 V	-	3 V	3 V	3 V	-	3 V
Nominal supply voltage	3.3 V	-	3.3 V	-	3.3 V	3.3 V	3.3 V	-	3.3 V
surface mount	YES	-	YES	-	YES	YES	YES	-	YES
technology	CMOS	-	CMOS	-	CMOS	CMOS	CMOS	-	CMOS
Temperature level	COMMERCIAL	-	INDUSTRIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	INDUSTRIAL
Terminal form	GULL WING	-	J BEND	-	GULL WING	J BEND	J BEND	-	GULL WING
Terminal pitch	0.65 mm	-	1.27 mm	-	0.65 mm	1.27 mm	1.27 mm	-	0.65 mm
Terminal location	DUAL	-	QUAD	-	DUAL	QUAD	QUAD	-	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
width	4.4 mm	-	11.5062 mm	-	4.4 mm	11.5062 mm	11.5062 mm	-	4.4 mm

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