PIC32MZ0512ECF064T-E/MR datasheet, PDF

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PIC32MZ0512ECF064T-E/MR: DescriptionMICROCONTROLLER; CategoryThe embedded processor and controller Microcontrollers and processors; File Size12MB，658 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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PIC32MZ0512ECF064T-E/MR Overview

MICROCONTROLLER

PIC32MZ0512ECF064T-E/MR Parametric

Parameter Name	Attribute value
Objectid	1358856890
Reach Compliance Code	compliant
Country Of Origin	Thailand
ECCN code	3A991.A.2
YTEOL	7.85
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	64 MHz
DMA channel	YES
External data bus width
length	9 mm
Number of I/O lines	46
Number of terminals	64
PWM channel	YES
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
rom(word)	524288
speed	200 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	2.3 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	9 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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PIC32MZ Embedded

Connectivity (EC) Family

32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with

Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog

Operating Conditions

• 2.3V to 3.6V, -40ºC to +85ºC, DC to 200 MHz

• 2.3V to 3.6V, -40ºC to +105ºC, DC to 180 MHz

• 2.3V to 3.6V, -40ºC to +125ºC (Planned)

Advanced Analog Features

•

10-bit ADC resolution and up to 48 analog inputs

Flexible and independent ADC trigger sources

Two comparators with 32 programmable voltage references

Temperature sensor with ±2ºC accuracy

Core: 200 MHz (up to 330 DMIPS) microAptiv™

16 KB I-Cache, 4 KB D-Cache

MMU for optimum embedded OS execution

microMIPS™ mode for up to 35% smaller code size

DSP-enhanced core:

- Four 64-bit accumulators

- Single-cycle MAC, saturating and fractional math

• Code-efficient (C and Assembly) architecture

•

Communication Interfaces

• Two CAN modules (with dedicated DMA channels):

- 2.0B Active with DeviceNet™ addressing support

• Six UART modules (25 Mbps):

- Supports LIN 1.2 and IrDA

protocols

• Six 4-wire SPI modules

• SQI configurable as an additional SPI module (50 MHz)

• Five I

C modules (up to 1 Mbaud) with SMBus support

• Parallel Master Port (PMP)

• Peripheral Pin Select (PPS) to enable function remap

Clock Management

•

0.9% internal oscillator

Programmable PLLs and oscillator clock sources

Fail-Safe Clock Monitor (FSCM)

Independent Watchdog Timers (WDT) and Deadman

Timer (DMT)

• Fast wake-up and start-up

Timers/Output Compare/Input Capture

•

Nine 16-bit or up to four 32-bit timers/counters

Nine Output Compare (OC) modules

Nine Input Capture (IC) modules

PPS to enable function remap

Real-Time Clock and Calendar (RTCC) module

Power Management

• Low-power modes (Sleep and Idle)

• Integrated Power-on Reset and Brown-out Reset

Input/Output

• 5V-tolerant pins with up to 32 mA source/sink

• Selectable open drain, pull-ups, and pull-downs

• External interrupts on all I/O pins

Memory Interfaces

• 50 MHz External Bus Interface (EBI)

• 50 MHz Serial Quad Interface (SQI)

Audio and Graphics Interfaces

•

Graphics interfaces: EBI or PMP

Audio data communication: I

S, LJ, and RJ

Audio control interfaces: SPI and I

C™

Audio master clock: Fractional clock frequencies with USB

synchronization

Qualification and Class B Support

•

AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) Planned

AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) Planned

Class B Safety Library, IEC 60730

Back-up internal oscillator

Debugger Development Support

•

In-circuit and in-application programming

4-wire MIPS

Enhanced JTAG interface

Unlimited software and 12 complex breakpoints

IEEE 1149.2-compatible (JTAG) boundary scan

Non-intrusive hardware-based instruction trace

High-Speed (HS) Communication Interfaces

(with Dedicated DMA)

• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller

• 10/100 Mbps Ethernet MAC with MII and RMII interface

Security Features

• Crypto Engine with a RNG for data encryption/decryption

and authentication (AES, 3DES, SHA, MD5, and HMAC)

• Advanced memory protection:

- Peripheral and memory region access control

Software and Tools Support

•

C/C++ compiler with native DSP/fractional support

MPLAB

Harmony Integrated Software Framework

TCP/IP, USB, Graphics, and mTouch™ middleware

MFi, Android™, and Bluetooth

audio frameworks

FreeRTOS™, OPENRTOS

μC/OS™,

and other popular

RTOS kernels

Direct Memory Access (DMA)

• Eight channels with automatic data size detection

• Programmable Cyclic Redundancy Check (CRC)

Packages

Type

Pin Count

I/O Pins (up to)

Contact/Lead Pitch

Dimensions

QFN

0.50 mm

9x9x0.9 mm

0.50 mm

10x10x1 mm

TQFP

100

0.40 mm

12x12x1 mm

0.50 mm

14x14x1 mm

144

120

0.40 mm

16x16x1 mm

VTLA

124

0.50 mm

9x9x0.9 mm

LQFP

144

120

0.50 mm

20x20x1.40 mm



2013-2014 Microchip Technology Inc.

Preliminary

DS60001191C-page 1

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