STB9NK90Z, STF9NK90Z
STP9NK90Z, STW9NK90Z
N-channel 900 V, 1.1
Ω,
8 A, TO-220, TO-220FP, D
2
PAK, TO-247
Zener-protected SuperMESH™ Power MOSFET
Features
Type
STB9NK90Z
STW9NK90Z
STP9NK90Z
STF9NK90Z
■
■
■
V
DSS
R
DS(on)
max.
I
D
Pw
160 W
3
1
2
3
1
900V
<1.3Ω
8A
160 W
160 W
40 W
TO-220
D²PAK
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
TO-247
2
1
3
3
TO-220FP
1
2
Application
■
Switching applications
Figure 1.
Internal schematic diagram
D(2)
Description
The SuperMESH™ series is obtained through an
optimization of STMicroelectronics’ well-
established strip-based PowerMESH™ layout. In
addition to pushing on-resistance significantly
lower, it also ensures very good dv/dt capability
for the most demanding applications. This series
complement STs’ full range of high voltage power
MOSFETs.
G(1)
S(3)
AM01476v1
Table 1.
Device summary
Marking
B9NK90
F9NK90Z
P9NK90Z
W9NK90Z
Package
D²PAK
TO-220FP
TO-220
TO-247
Tube
Packaging
Tape and reel
Order codes
STB9NK90Z
STF9NK90Z
STP9NK90Z
STW9NK90Z
May 2010
Doc ID 9479 Rev 7
1/17
www.st.com
17
Contents
STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
4
5
6
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
Doc ID 9479 Rev 7
STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Value
Parameter
TO-220, D²PAK
TO-247
900
± 30
8
5
32
160
1.28
4
4.5
--
2500
8
(1)
5
(1)
32
(1)
40
0.32
Unit
TO-220FP
V
V
A
A
A
W
W/°C
KV
V/ns
V
V
DS
V
GS
I
D
I
D
I
DM(2)
P
TOT
Drain-source voltage (V
GS
= 0)
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
=100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Derating Factor
Vesd(G-S) G-S ESD (HBM C=100 pF, R=1.5 kΩ)
dv/dt
(3)
V
ISO
T
J
T
stg
Peak diode recovery voltage slope
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t=1s;T
C
=25°C)
Operating junction temperature
Storage temperature
-55 to 150
°C
1. Limited only by maximum temperature allowed
2. Pulse width limited by safe operating area
3. I
SD
≤
10 A, di/dt
≤
200 A/µs,V
DD
≤
V
(BR)DSS
, T
j
≤
T
Jmax.
Table 3.
Symbol
Thermal data
Value
Parameter
TO-220
TO-220FP TO-247
D²PAK
0.78
62.5
300
3.1
0.78
50
Unit
R
thj-case
R
thj-a
T
l
Thermal resistance junction-case max
Thermal resistance junction-ambient max
Maximum lead temperature for soldering
purpose
°C/W
°C/W
°C
Table 4.
Symbol
I
AR
E
AS
Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj max.)
Single pulse avalanche energy (starting Tj=25 °C,
I
D
= I
AR
, V
DD
= 50 V)
(see Figure 22)(see Figure 23)
Doc ID 9479 Rev 7
Value
8
300
Unit
A
mJ
3/17
Electrical characteristics
STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z
2
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 5.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On/off states
Parameter
Drain-source breakdown
voltage
Zero gate voltage drain
current (V
GS
= 0)
Gate body leakage current
(V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
= 1 mA, V
GS
= 0
V
DS
= max rating,
V
DS
= max rating @125 °C
V
GS
= ± 20 V, V
DS
= 0
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 3.6 A
3
3.75
1.1
Min.
900
1
50
±
10
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
4.5
1.3
Table 6.
Symbol
C
iss
C
oss
C
rss
C
oss eq(1)
Q
g
Q
gs
Q
gd
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
Min.
Typ.
2115
190
40
115
72
14
38
Max.
Unit
pF
pF
pF
pF
nC
nC
nC
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0
-
-
V
GS
= 0, V
DS
= 0 to 720 V
V
DD
= 720 V, I
D
= 8 A
V
GS
=10 V
Figure 20
-
-
-
-
1. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
4/17
Doc ID 9479 Rev 7
STB9NK90Z, STF9NK90Z, STP9NK90Z, STW9NK90Z
Electrical characteristics
Table 7.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on delay time
Rise Time
Turn-off delay time
Fall time
Test conditions
V
DD
= 450 V, I
D
= 4 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
Figure 19
Figure 24
Min.
-
Typ.
22
13
55
28
Max.
-
Unit
ns
ns
ns
ns
-
-
Table 8.
Symbol
I
SD
I
SDM(1)
V
SD(2)
t
rr
Q
rr
I
RRM
Source drain diode
Parameter
Source-drain current
-
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 8 A, V
GS
=0
I
SD
= 8 A,
di/dt = 100 A/µs,
V
DD
= 50 V, Tj = 150 °C
Figure 21
-
950
10
21
32
1.6
A
V
ns
µC
A
Test conditions
Min
Typ.
Max
8
Unit
A
-
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300 µs, duty cycle 1.5%
Table 9.
Symbol
BV
GSO
Gate-source Zener diode
Parameter
Test conditions
Min.
30
Typ.
-
Max.
Unit
V
Gate-source breakdown voltage I
GS
= ±1 mA(open drain)
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
Doc ID 9479 Rev 7
5/17
MCU
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