MPC8313CVRADDC datasheet, PDF - EEWORLD Datasheet

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MPC8313CVRADDC: Descriptionmicroprocessors - mpu 8313 rev2.2 NO enc ext; Categorysemiconductor Other integrated circuit (IC); File Size1MB，99 Pages; ManufacturerFREESCALE (NXP); Environmental Compliance

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Freescale Semiconductor

Datasheet: Technical Data

Document Number: MPC8313EEC

Rev. 4, 11/2011

MPC8313E

PowerQUICC II Pro Processor

Hardware Specifications

This document provides an overview of the MPC8313E

PowerQUICC™ II Pro processor features, including a block

diagram showing the major functional components. The

MPC8313E is a cost-effective, low-power, highly integrated

host processor that addresses the requirements of several

printing and imaging, consumer, and industrial applications,

including main CPUs and I/O processors in printing systems,

networking switches and line cards, wireless LANs

(WLANs), network access servers (NAS), VPN routers,

intelligent NIC, and industrial controllers. The MPC8313E

extends the PowerQUICC™ family, adding higher CPU

performance, additional functionality, and faster interfaces

while addressing the requirements related to time-to-market,

price, power consumption, and package size.

NOTE

The information in this document is accurate for

revisions 1.0, 2.x, and later. See

Section 23.1, “Part

Numbers Fully Addressed by this Document.”

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 14

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Ethernet: Three-Speed Ethernet, MII Management . 21

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 36

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 47

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 63

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

System Design Information . . . . . . . . . . . . . . . . . . . 87

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 93

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

Overview

The MPC8313E incorporates the e300c3 core, which includes 16 Kbytes of L1 instruction and data caches

and on-chip memory management units (MMUs). The MPC8313E has interfaces to dual enhanced

three-speed 10/100/1000 Mbps Ethernet controllers, a DDR1/DDR2 SDRAM memory controller, an

enhanced local bus controller, a 32-bit PCI controller, a dedicated security engine, a USB 2.0 dual-role

controller and an on-chip high-speed PHY, a programmable interrupt controller, dual I

C controllers, a

4-channel DMA controller, and a general-purpose I/O port. This figure shows a block diagram of the

MPC8313E.

DUART

Dual I

Timers

GPIO

e300c3 Core w/FPU and

Power Management

Interrupt

Controller

16-KB

I-Cache

16-KB

D-Cache

Local Bus,

SPI

DDR1/DDR2

Controller

I/O Sequencer

(IOS)

PCI

DMA

Security Engine 2.2

USB 2.0

Host/Device/OTG

ULPI

On-Chip

FS PHY

Gb Ethernet

MAC

Gb Ethernet

MAC

Note:

The MPC8313 does not include a security engine.

Figure 1. MPC8313E Block Diagram

The MPC8313E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded

from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES,

3DES, AES, SHA-1, and MD-5 algorithms.

1.1

MPC8313E Features

The following features are supported in the MPC8313E:

• Embedded PowerPC™ e300 processor core built on Power Architecture™ technology; operates at

up to 333 MHz.

• High-performance, low-power, and cost-effective host processor

• DDR1/DDR2 memory controller—one 16-/32-bit interface at up to 333 MHz supporting both

DDR1 and DDR2

• 16-Kbyte instruction cache and 16-Kbyte data cache, a floating point unit, and two integer units

• Peripheral interfaces such as 32-bit PCI interface with up to 66-MHz operation, 16-bit enhanced

local bus interface with up to 66-MHz operation, and USB 2.0 (high speed) with an on-chip PHY.

• Security engine provides acceleration for control and data plane security protocols

• Power management controller for low-power consumption

• High degree of software compatibility with previous-generation PowerQUICC processor-based

designs for backward compatibility and easier software migration

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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