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74HC273D,652

Description
flip flops octal D F/F W/reset
Categorylogic    logic   
File Size148KB,21 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric View All

74HC273D,652 Overview

flip flops octal D F/F W/reset

74HC273D,652 Parametric

Parameter NameAttribute value
Brand NameNXP Semiconductor
Is it Rohs certified?conform to
Parts packaging codeSOP
package instruction7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20
Contacts20
Manufacturer packaging codeSOT163-1
Reach Compliance Codecompliant
ECCN codeEAR99
seriesHC/UH
JESD-30 codeR-PDSO-G20
length12.8 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup20000000 Hz
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingBULK PACK
Peak Reflow Temperature (Celsius)260
power supply2/6 V
propagation delay (tpd)225 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL/PALLADIUM/GOLD (NI/PD/AU)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width7.5 mm
minfmax24 MHz
Base Number Matches1
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 10 June 2013
Product data sheet
1. General description
The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device
features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of
their corresponding Dn inputs that meet the set-up and hold time requirements on the
LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently
of clock and data inputs. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC273: CMOS level
For 74HCT273: TTL level
Common clock and master reset
Eight positive edge-triggered D-type flip-flops
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC273N
74HCT273N
74HC273D
74HCT273D
74HC273DB
74HCT273DB
40 C
to +125
C
SSOP20
plastic shrink small outline package; 20 leads; body width
5.3 mm
SOT339-1
40 C
to +125
C
SO20
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
40 C
to +125
C
DIP20
Description
plastic dual in-line package; 20 leads (300 mil)
Version
SOT146-1
Type number
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