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MT8VDDT3264HDY-265A1

Description
DDR DRAM Module, 32MX64, 0.75ns, CMOS, SODIMM-200
Categorystorage    storage   
File Size637KB,32 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance  
Download Datasheet Parametric View All

MT8VDDT3264HDY-265A1 Overview

DDR DRAM Module, 32MX64, 0.75ns, CMOS, SODIMM-200

MT8VDDT3264HDY-265A1 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeMODULE
package instructionDIMM,
Contacts200
Reach Compliance Codecompliant
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time0.75 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N200
JESD-609 codee4
memory density2147483648 bit
Memory IC TypeDDR DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals200
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX64
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceGold (Au)
Terminal formNO LEAD
Terminal locationDUAL
Maximum time at peak reflow temperature30
128MB, 256MB, 512MB, 1GB (x64, DR)
200-PIN DDR SODIMM
DDR SDRAM SMALL-
OUTLINE DIMM
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 128MB (16 Meg x 64), 256MB (32 Meg x 64), 512MB
(64 Meg x 64), or 1GB (128 Meg x 64)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes
• 15.6µs (128MB), 7.8125µs (256MB, 512MB, and
1GB) maximum average periodic refresh interval
• Gold edge contacts
MT8VDDT1664HD – 128MB
MT8VDDT3264HD – 256MB
MT8VDDT6464HD – 512MB
MT8VDDT12864HD – 1GB (ADVANCE
)
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 200-Pin SODIMM (MO-224)
1.25in. (31.75mm)
OPTIONS
MARKING
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
1
• Memory Clock, Speed, CAS Latency
2
6ns (166 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• PCB
1.25in. (31.75mm)
NOTE:
2. CL = CAS (READ) Latency
G
Y
-335
-262
1
-26A
1
-265
1. Contact Micron for product availability.
Table 1:
Address Table
128MB
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (16 Meg x 16)
512 (A0–A8)
2 (S0#, S1#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (32 Meg x 16)
1K (A0–A9)
2 (S0#, S1#)
1GB
8K
16K (A0–A13)
4 (BA0, BA1)
1Gb (64 Meg x 16)
1K (A0–A9)
2 (S0#, S1#)
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (8 Meg x 16)
512 (A0–A8)
2 (S0#, S1#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef80765fab, source: 09005aef806e1d28
DD8C16_32_64_128x64HDG.fm - Rev. B 9/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
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