White Electronic Designs
16Mx72 Registered DDR SDRAM
FEATURES
Registered for enhanced performance of bus
speeds of 200, 225, and 250 MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable I
OL
/I
OH
option
Auto precharge option
W3E16M72SR-XBX
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 72
Weight: W3E16M72SR-XBX - 2.5 grams typical
BENEFITS
47% SPACE SAVINGS
Glueless Connection to PCI Bridge/Memory
Controller
Reduced part count
Reduced I/O count
• 49% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 72 density (contact factory
for information)
* This product is subject to change without notice.
Monolithic Solution
22.3
11.9
66
TSOP
22.3
66
TSOP
12.6
8.3
48
TSOP
Actual Size
S
A
V
I
N
G
S
11.9
11.9
11.9
White Electronic Designs
W3E16M72SR-XBX
25
22.3
66
TSOP
66
TSOP
66
TSOP
12.6
48
TSOP
32
Area
I/O
Count
February 2005
Rev. 2
5 x 265mm2 + 2 x 105mm2 = 1536mm2
5 x 66 pins + 2 x 48 = 426 pins
1
800mm2
219 Balls
47%
49%
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 1 – PIN CONFIGURATION
Top View
W3E16M72SR-XBX
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ1
2
DQ0
3
DQ14
4
DQ15
5
V
SS
6
V
SS
7
A9
8
A10
9 10 11 12 13 14 15 16
A11
A8
V
CCQ
V
CCQ
DQ16
DQ17
DQ31
VSS
DQ2
DQ12
DQ13
V
SS
V
SS
A0
A7
A6
A1
V
CC
V
CC
DQ18
DQ19
DQ29
DQ30
DQ3
DQ4
DQ10
DQ11
V
CC
V
CC
A2
A5
A4
A3
V
SS
V
SS
DQ20
DQ21
DQ27
DQ28
DQ6
DQ5
DQ8
DQ9
V
CCQ
V
CCQ
A12
DNU
DNU
DNU
V
SS
V
SS
DQ22
DQ23
DQ26
DQ25
DQ7
DM0
V
CC
DM1
DQS7
DQS0
DQS1
BA0
BA1
DQS2
DQS3
V
REF
DM2
V
SS
NC
DQ24
CAS#
WE#
V
CC
CK0
DQS6
RCK0
RCK0B
V
SS
DM3
CK1
CS#
RAS#
V
CC
CKE
CK0#
RCK1
RCK1B
V
SS
CK1#
NC
V
SS
V
SS
V
CC
V
CCQ
V
SS
V
CC
V
SS
V
SS
V
CCQ
V
CC
V
SS
V
SS
V
CC
V
CCQ
V
SS
V
CC
V
SS
V
SS
V
CCQ
V
CC
CK3#
NC
V
CC
NC
DQS8
CK2#
NC
V
SS
NC
NC
NC
CK3
V
CC
NC
NC
DQS4
CK2
V
SS
RESET#
RV
REF
DQ56
DM7
V
CC
NC
DM6
NC
DM9
CK4
NC
NC
NC
NC
DM5
V
SS
DM4
DQ39
DQ57
DQ58
DQ55
DQ54
DQS9
CK4#
DQ73
DQ72
DQ71
DQ70
DM8
DQS5
DQ41
DQ40
DQ37
DQ38
DQ60
DQ59
DQ53
DQ52
V
SS
V
SS
DQ75
DQ74
DQ69
DQ68
V
CC
V
CC
DQ43
DQ42
DQ36
DQ35
DQ62
DQ61
DQ51
DQ50
V
CC
V
CC
DQ77
DQ76
DQ67
DQ66
V
SS
V
SS
DQ45
DQ44
DQ34
DQ33
V
SS
DQ63
DQ49
DQ48
V
CCQ
V
CCQ
DQ79
DQ78
DQ65
DQ64
V
SS
V
SS
DQ47
DQ46
DQ32
V
CC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades. Pin D8 will be A13, D9 will be A14, and D10 will be A15 as needed.
NC = Not Connected Internally.
February 2005
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3E16M72SR-XBX
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
CS
B
#
WE
B
#
RAS
B
#
CAS
B
#
CS# WE# RAS# CAS#
V
REF
A
0-12
BA
0-1
CK
0
CK
0
#
CKE
B
DM
0
DM
1
DQS
0
DQS
1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
V
REF
U0
RCK
0
RCK
0B
CS# WE# RAS# CAS#
A
0-12
BA
0
-
1
SSTV16857
V
REF
A
0-12
BA
0-1
CK
1
CK
1
#
CKE
B
DM
2
DM
3
DQS
2
DQS
3
RCK
1
RCK
1B
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
U5
U1
RV
REF
RESET#
V
REF
RESET#
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
16
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
31
CS# WE# RAS# CAS#
CAS#
RAS#
WE#
CS#
CKE
SSTV16857
CAS
B
#
RAS
B
#
WE
B
#
CS
B
#
CKE
B
#
CK
2
CK
2
#
CKE
B
DM
4
DM
5
DQS
4
DQS
5
V
REF
A
0-12
BA
0-1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
32
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
47
U6
U2
V
REF
RESET#
CS# WE# RAS# CAS#
V
REF
A
0-12
CK
3
CK
3
#
CKE
B
DM
6
DM
7
DQS
6
DQS
7
BA
0-1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
U3
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
48
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
63
CS# WE# RAS# CAS#
V
REF
A
0-12
CK
4
CK
4
#
CKE
B
DM
8
DM
9
DQS
8
DQS
9
BA
0-1
CK
CK#
CKE
DQML
DQMH
DQSL
DQSH
U4
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
64
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
79
February 2005
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 128MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
and by the memory contoller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
W3E16M72SR-XBX
The pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high
effective bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to V
CC
and V
CCQ
simultaneously, and
then to V
REF
(and to the system V
TT
). V
TT
must be applied
after V
CCQ
to avoid device latch-up, which may cause
permanent damage to the device. V
REF
can be applied any
time after V
CCQ
but is expected to be nominally coincident
with V
TT
. Except for CKE, inputs are not recognized as
valid until after V
REF
is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after V
CC
is applied.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.
February 2005
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
Once the 200µs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (t
RFC
must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
W3E16M72SR-XBX
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the
burst length is set to two; by A2-Ai when the burst length
is set to four (where Ai is the most significant column
address for a given configuration); and by A3-Ai when the
burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to
both READ and WRITE bursts.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The
Mode Register must be loaded (reloaded) when all banks
are idle and no bursts are in progress, and the controller
must wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge
n,
and the
latency is
m
clocks, the data will be available by clock edge
n+m.
Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
February 2005
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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