MT45W2MW16BGB-708 WT TR datasheet, PDF

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MT45W2MW16BGB-708 WT TR: DescriptionPSRAM（伪 SRAM）存储器 IC 32Mb（2M x 16）并联 70 ns 54-VFBGA（6x8）; Categorysemiconductor memory; File Size2MB，61 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT45W2MW16BGB-708 WT TR Overview

PSRAM（伪 SRAM）存储器 IC 32Mb（2M x 16）并联 70 ns 54-VFBGA（6x8）

MT45W2MW16BGB-708 WT TR Parametric

Parameter Name	Attribute value
category
Maker	Micron Technology
series	-
Package	卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带
memory type	Volatile
memory format	PSRAM
technology	PSRAM (pseudo-SRAM)
storage	32Mb（2M x 16）
memory interface	in parallel
Write cycle time - words, pages	70ns
interview time	70 ns
Voltage - Power supply	1.7V ~ 1.95V
Operating temperature	-30°C ~ 85°C（TC）
Installation type	surface mount type
Package/casing	54-VFBGA
Supplier device packaging	54-VFBGA（6x8）
Basic product number	MT45W2MW16

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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Features

Async/Page/Burst

CellularRAM

1.0 Memory

MT45W2MW16BGB

Features

• Single device supports asynchronous, page, and

burst operations

• Random access time: 70ns

• V

, V

Q voltages

–

1.7–1.95V V

–

1.7–3.6V V

• Page mode read access

–

16-word page size

–

Interpage read access: 70ns

–

Intrapage read access: 20ns

• Burst mode write access: continuous burst

• Burst mode read access

–

4, 8, or 16 words or continuous burst

–

MAX clock rate: 104 MHz (

CLK = 9.62ns)

–

Burst initial latency: 38.5ns (4 clocks) at 104 MHz

–

ACLK: 7ns at 104 MHz

• Low power consumption

–

Asynchronous read: <20mA

–

Intrapage read: <15mA

–

Intrapage read initial access, burst read:

(38.5ns [4 clocks] at 104 MHz) <40mA

–

Continuous burst read: <25mA

–

Standby: <110µA

–

Deep power-down: <10µA (TYP at 25°C)

• Low-power features

–

Temperature-compensated refresh (TCR)

–

On-chip temperature sensor

–

Partial-array refresh (PAR)

–

Deep power-down (DPD) mode

Figure 1:

54-Ball VFBGA Ball Assignment

LB#

DQ8

DQ9

OE#

UB#

DQ10

A17

A14

A12

ADV#

A16

A15

A13

A10

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

CRE

DQ0

DQ2

VCC

VSS

DQ6

DQ7

A20

Q DQ11

Q DQ12

DQ14 DQ13

DQ15

A18

WAIT

A19

CLK

Top view

(Ball down)

Options (continued)

• Standby power

–

Standard

• Low power

• Operating temperature range

–

Wireless (–30°C to +85°C)

–

Industrial (–40°C to +85°C)

Designator

None

Options

• Configuration

–

2 Meg x 16

• Package

–

54-ball VFBGA (“green”)

• Access time

–

70ns

• Frequency

–

80 MHz

–

104 MHz

PDF: 09005aef82832fa2/Source: 09005aef82832f5f

32mb_burst_cr1_0_p24z_1.fm - Rev. E 9/08 EN

Designator

MT45W2MW16B

-70

Notes: 1. –30°C exceeds the CellularRAM Workgroup

1.0 specification of –25°C.

2. Contact factory for availability.

Part Number Example:

MT45W2MW16BGB-701WT

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .28

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Latency Counter (BCR[13:11]) Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

PDF: 09005aef82832fa2/Source: 09005aef82832f5f

32mb_burst_c1_0_p24zTOC.fm - Rev. E 9/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

List of Figures

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Figure 47:

Figure 48:

Figure 49:

54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Functional Block Diagram – 2 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Mode READ (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Burst Mode WRITE (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Asynchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation . . . . . .20

Synchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation . . . . . . .21

Asynchronous Mode Configuration Register READ Followed by READ ARRAY Operation . . . . . . .22

Synchronous Mode Configuration Register READ Followed by READ ARRAY Operation . . . . . . . .23

Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Latency Counter (Variable Latency, No Refresh Collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Typical Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Single-Access Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Output Delay in Continuous Burst READ with BCR[8] = 0 for End-of-Row Condition . . . . . . . . . . .46

CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Output Delay in Continuous Burst WRITE with BCR[8] = 0 for End-of-Row Condition . . . . . . . . . .52

Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Asynchronous WRITE Followed by Burst READ with ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Asynchronous WRITE Followed by Asynchronous READ with ADV# LOW . . . . . . . . . . . . . . . . . . . . .58

Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

PDF: 09005aef82832fa2/Source: 09005aef82832f5f

32mb_burst_c1_0_p24zLOF.fm - Rev. E 9/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

List of Tables

Table 1:

Table 2:

Table 3:

Table 4:

Table 5:

Table 6:

Table 7:

Table 8:

Table 9:

Table 10:

Table 11:

Table 12:

Table 13:

Table 14:

Table 15:

Table 16:

VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Bus Operations: Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Bus Operations: Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

32Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Partial-Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

PDF: 09005aef82832fa2/Source: 09005aef82832f5f

32mb_burst_c1_0_p24zLOT.fm - Rev. E 9/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

General Description

Micron

CellularRAM

is a high-speed, CMOS PSRAM memory device developed for

low-power, portable applications. The MT45W2MW16BGB is a 32Mb DRAM core

device organized as 2 Meg x 16 bits. This device includes an industry-standard

burst mode Flash interface that dramatically increases READ/WRITE bandwidth

compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings.

For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans-

parent self refresh mechanism. The hidden refresh requires no additional support from

the system memory controller and has no significant impact on device READ/WRITE

performance.

Two user-accessible control registers define device operation. The bus configuration

bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh

configuration register (RCR) is used to control how refresh is performed on the DRAM

array. These registers are automatically loaded with default settings during power-up

and can be updated anytime during normal operation.

Special attention has been focused on standby current consumption during self refresh.

CellularRAM products include three system-accessible mechanisms to minimize

standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM

array that contains essential data. Temperature-compensated refresh (TCR) uses an on-

chip sensor to adjust the refresh rate to match the device temperature. The refresh rate

decreases at lower temperatures to minimize current consumption during standby.

Deep power-down (DPD) halts the REFRESH operation altogether and is used when no

vital information is stored in the device. These three refresh mechanisms are accessed

through the RCR.

PDF: 09005aef82832fa2/Source: 09005aef82832f5f

32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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