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MT48H8M16LFB4-6 IT:K

Description
SDRAM - 移动 LPSDR 存储器 IC 128Mb(8M x 16) 并联 166 MHz 5 ns 54-VFBGA(8x8)
Categorysemiconductor    memory   
File Size2MB,86 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT48H8M16LFB4-6 IT:K Overview

SDRAM - 移动 LPSDR 存储器 IC 128Mb(8M x 16) 并联 166 MHz 5 ns 54-VFBGA(8x8)

MT48H8M16LFB4-6 IT:K Parametric

Parameter NameAttribute value
category
MakerMicron Technology
series-
Packagetray
memory typeVolatile
memory formatDRAM
technologySDRAM - Mobile LPSDR
storage128Mb(8M x 16)
memory interfacein parallel
Write cycle time - words, pages15ns
Voltage - Power supply1.7V ~ 1.95V
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount type
Package/casing54-VFBGA
Supplier device packaging54-VFBGA(8x8)
Clock frequency166 MHz
interview time5 ns
Basic product numberMT48H8M16
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
Features
Mobile Low-Power SDR SDRAM
MT48H8M16LF – 2 Meg x 16 x 4 banks
MT48H4M32LF – 1 Meg x 32 x 4 banks
Features
• V
DD
/V
DDQ
= 1.7–1.95V
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• 4 internal banks for concurrent operation
• Programmable burst lengths (BL): 1, 2, 4, 8, and con-
tinuous
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive strength (DS)
• 64ms refresh period
Options
• V
DD
/V
DDQ
: 1.8V/1.8V
• Addressing
– Standard addressing option
• Configuration
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
– 4 Meg x 32 (1 Meg x 32 x 4 banks)
• Plastic “green” packages
– 54-ball VFBGA (8mm x 8mm)
1
– 90-ball VFBGA (8mm x 13mm)
2
• Timing: cycle time
– 6ns at CL = 3
– 7.5ns at CL = 3
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
• Revision
Notes:
Marking
H
LF
8M16
4M32
B4
B5
-6
-75
None
IT
:K
1. Available only for x16 configuration.
2. Available only for x32 configuration.
Table 1: Configuration Addressing
Architecture
Number of banks
Bank address balls
Row address balls
Column address balls
8 Meg x 16
4
BA0, BA1
A[11:0]
A[8:0]
4 Meg x 32
4
BA0, BA1
A[11:0]
A[7:0]
Table 2: Key Timing Parameters
Speed
Grade
-6
-75
Note:
Clock Rate (MHz)
CL = 2
104
104
CL = 3
166
133
Access Time
CL = 2
8ns
8ns
CL = 3
5ns
5.4ns
1. CL = CAS (READ) latency
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
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