MT49H16M18CFM-5 IT datasheet, PDF

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MT49H16M18CFM-5 IT: DescriptionDRAM 存储器 IC 288Mb（16M x 18）并联 200 MHz 20 ns 144-µBGA（18.5x11）; Categorysemiconductor memory; File Size6MB，74 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT49H16M18CFM-5 IT Overview

DRAM 存储器 IC 288Mb（16M x 18）并联 200 MHz 20 ns 144-µBGA（18.5x11）

MT49H16M18CFM-5 IT Parametric

Parameter Name	Attribute value
category
Maker	Micron Technology
series	-
Package	tray
memory type	Volatile
memory format	DRAM
technology	DRAM
storage	288Mb（16M x 18）
memory interface	in parallel
Write cycle time - words, pages	-
Voltage - Power supply	1.7V ~ 1.9V
Operating temperature	-40°C ~ 85°C（TA）
Installation type	surface mount type
Package/casing	144-TFBGA
Supplier device packaging	144-µBGA（18.5x11）
Clock frequency	200 MHz
interview time	20 ns
Basic product number	MT49H16M18

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288Mb: x18 SIO RLDRAM 2

Features

SIO RLDRAM 2

MT49H16M18C – 16 Meg x 18 x 8 banks

Features

• 533 MHz DDR operation (1.067 Gb/s/pin data rate)

• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock

frequency)

• Organization

– 16 Meg x 18 separate I/O

– 8 banks

Cyclic bank switching for maximum bandwidth

Reduced cycle time (15ns at 533 MHz)

Nonmultiplexed addresses (address multiplexing

option available)

SRAM-type interface

Programmable READ latency (RL), row cycle time,

and burst sequence length

Balanced READ and WRITE latencies in order to op-

timize data bus utilization

Data mask for WRITE commands

Differential input clocks (CK, CK#)

Differential input data clocks (DKx, DKx#)

On-die DLL generates CK edge-aligned data and

output data clock signals

Data valid signal (QVLD)

32ms refresh (8K refresh for each bank; 64K refresh

command must be issued in total each 32ms)

HSTL I/O (1.5V or 1.8V nominal)

25–60Ω

matched impedance outputs

2.5V V

EXT

, 1.8V V

, 1.5V or 1.8V V

DDQ

I/O

On-die termination (ODT) R

Options

Marking

-18

-25E

-25

-33

16M18

None

•

• Clock cycle timing

– 1.875ns @

RC = 15ns

– 2.5ns @

RC = 15ns

– 2.5ns @

RC = 20ns

– 3.3ns @

RC = 20ns

• Configuration

– 16 Meg x 18

• Operating temperature range

– Commercial (0° to +95°C)

– Industrial (T

= –40°C to +95°C; T

–40°C to +85°C)

• Package

– 144-ball µBGA

– 144-ball µBGA (Pb-free)

– 144-ball FBGA

– 144-ball FBGA (Pb-free)

• Revision

Note:

1. Not all options listed can be combined to

define an offered product. Use the part cat-

alog search on

micron.com

for available of-

ferings.

PDF: 09005aef80a41b59

288Mb_RLDRAM_2_SIO.pdf - Rev. J 10/15 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

288Mb: x18 SIO RLDRAM 2

Features

Contents

General Description ......................................................................................................................................... 7

Functional Block Diagrams .............................................................................................................................. 8

Ball Assignments and Descriptions ................................................................................................................... 9

Package Dimensions ....................................................................................................................................... 11

Electrical Specifications – I

.......................................................................................................................... 13

Absolute Maximum Ratings ............................................................................................................................ 16

AC and DC Operating Conditions .................................................................................................................... 16

Input Slew Rate Derating ................................................................................................................................ 19

Temperature and Thermal Impedance ............................................................................................................ 26

Commands .................................................................................................................................................... 29

MODE REGISTER SET (MRS) Command ......................................................................................................... 30

Configuration Tables .................................................................................................................................. 32

Burst Length (BL) ....................................................................................................................................... 32

Address Multiplexing .................................................................................................................................. 34

DLL RESET ................................................................................................................................................. 34

Drive Impedance Matching ........................................................................................................................ 34

On-Die Termination (ODT) ......................................................................................................................... 35

READ Command ............................................................................................................................................ 36

WRITE Command .......................................................................................................................................... 37

AUTO REFRESH (AREF) Command ................................................................................................................. 38

INITIALIZATION Operation ............................................................................................................................ 39

WRITE Operations .......................................................................................................................................... 42

READ Operations ........................................................................................................................................... 46

AUTO REFRESH Operation ............................................................................................................................. 51

Operations with On-Die Termination .............................................................................................................. 52

Multiplexed Address Mode .............................................................................................................................. 55

Command Description ............................................................................................................................... 55

Power-Up/Initialization Sequence .............................................................................................................. 56

Mode Register ............................................................................................................................................ 57

Address Mapping ....................................................................................................................................... 58

Configuration Tables .................................................................................................................................. 58

REFRESH Command in Multiplexed Address Mode ..................................................................................... 59

IEEE 1149.1 Serial Boundary Scan Test Access Port ........................................................................................... 63

Disabling the Serial Boundary Scan Test Access Port .................................................................................... 63

Test Access Port (TAP) ..................................................................................................................................... 63

Test Clock (TCK) ......................................................................................................................................... 63

Test Mode Select (TMS) .............................................................................................................................. 63

Test Data-In (TDI) ...................................................................................................................................... 64

Test Data-Out (TDO) .................................................................................................................................. 64

TAP Controller ................................................................................................................................................ 64

Test-Logic-Reset ......................................................................................................................................... 64

Run-Test/Idle ............................................................................................................................................. 64

Select-DR-Scan .......................................................................................................................................... 64

Capture-DR ................................................................................................................................................ 64

Shift-DR ..................................................................................................................................................... 64

Exit1-DR, Pause-DR, and Exit2-DR .............................................................................................................. 65

Update-DR ................................................................................................................................................. 65

Instruction Register States .......................................................................................................................... 65

TAP Reset ....................................................................................................................................................... 66

TAP Registers ................................................................................................................................................. 66

PDF: 09005aef80a41b59

288Mb_RLDRAM_2_SIO.pdf - Rev. J 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

288Mb: x18 SIO RLDRAM 2

Features

Instruction Register ....................................................................................................................................

Bypass Register ..........................................................................................................................................

Boundary Scan Register ..............................................................................................................................

Identification (ID) Register ..........................................................................................................................

TAP Instruction Set .........................................................................................................................................

EXTEST ......................................................................................................................................................

IDCODE .....................................................................................................................................................

SAMPLE/PRELOAD ....................................................................................................................................

CLAMP ......................................................................................................................................................

High-Z .......................................................................................................................................................

BYPASS ......................................................................................................................................................

Reserved for Future Use ..............................................................................................................................

PDF: 09005aef80a41b59

288Mb_RLDRAM_2_SIO.pdf - Rev. J 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

288Mb: x18 SIO RLDRAM 2

Features

List of Figures

Figure 1: 288Mb RLDRAM 2 SIO Part Numbers ................................................................................................. 2

Figure 2: State Diagram ................................................................................................................................... 7

Figure 3: 16 Meg x 18 Functional Block Diagram ............................................................................................... 8

Figure 4: 144-Ball µBGA ................................................................................................................................. 11

Figure 5: 144-Ball FBGA ................................................................................................................................. 12

Figure 6: Clock Input ..................................................................................................................................... 18

Figure 7: Nominal

AS/

CS/

DS and

AH/

CH/

DH Slew Rate ........................................................................... 22

Figure 8: Example Temperature Test Point Location ........................................................................................ 28

Figure 9: Mode Register Set ............................................................................................................................ 30

Figure 10: Mode Register Definition in Nonmultiplexed Address Mode ............................................................ 31

Figure 11: Read Burst Lengths ........................................................................................................................ 33

Figure 12: On-Die Termination-Equivalent Circuit .......................................................................................... 35

Figure 13: READ Command ........................................................................................................................... 36

Figure 14: WRITE Command ......................................................................................................................... 37

Figure 15: AUTO REFRESH Command ........................................................................................................... 38

Figure 16: Power-Up/Initialization Sequence ................................................................................................. 40

Figure 17: Power-Up/Initialization Flow Chart ................................................................................................ 41

Figure 18: WRITE Burst ................................................................................................................................. 42

Figure 19: Consecutive WRITE-to-WRITE ....................................................................................................... 43

Figure 20: WRITE-to-READ ............................................................................................................................ 44

Figure 21: WRITE – DM Operation ................................................................................................................. 45

Figure 22: Basic READ Burst Timing ............................................................................................................... 46

Figure 23: Consecutive READ Bursts (BL = 2) .................................................................................................. 47

Figure 24: Consecutive READ Bursts (BL = 4) .................................................................................................. 47

Figure 25: READ-to-WRITE ............................................................................................................................ 48

Figure 26: READ/WRITE Interleave ................................................................................................................ 49

Figure 27: Read Data Valid Window for x18 Device .......................................................................................... 50

Figure 28: AUTO REFRESH Cycle ................................................................................................................... 51

Figure 29: READ Burst with ODT .................................................................................................................... 52

Figure 30: READ-NOP-READ with ODT .......................................................................................................... 53

Figure 31: READ-to-WRITE with ODT ............................................................................................................ 54

Figure 32: Command Description in Multiplexed Address Mode ..................................................................... 55

Figure 33: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 56

Figure 34: Mode Register Definition in Multiplexed Address Mode .................................................................. 57

Figure 35: Burst REFRESH Operation with Multiplexed Addressing ................................................................. 59

Figure 36: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 59

Figure 37: WRITE-to-READ with Multiplexed Addressing ................................................................................ 60

Figure 38: Consecutive READ Bursts with Multiplexed Addressing ................................................................... 61

Figure 39: READ-to-WRITE with Multiplexed Addressing ................................................................................ 62

Figure 40: TAP Controller State Diagram ......................................................................................................... 65

Figure 41: TAP Controller Block Diagram ........................................................................................................ 65

Figure 42: JTAG Operation – Loading Instruction Code and Shifting Out Data .................................................. 70

Figure 43: TAP Timing ................................................................................................................................... 70

PDF: 09005aef80a41b59

288Mb_RLDRAM_2_SIO.pdf - Rev. J 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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