4432-T-B1 B 470 datasheet, PDF

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4432-T-B1 B 470: Descriptionseries 收发器 For Use With Si4432; CategoryTopical application Wireless rf/communication; File Size2MB，74 Pages; ManufacturerSilicon Labs; Websitehttps://www.silabs.com

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4432-T-B1 B 470 Overview

series 收发器 For Use With Si4432

4432-T-B1 B 470 Parametric

Parameter Name	Attribute value
category
Maker	Silicon Labs
series	EZRadioPRO®
Package	box
type	transceiver
frequency	470MHz
Supporting use/related products	Si4432
What's included	plate

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Si4430/31/32-B1

Si4430/31/32 ISM T

RANSCEIVER

Features



Frequency Range



240–930 MHz (Si4431/32)



900–960 MHz (Si4430)

Sensitivity = –121 dBm

Output power range



+20 dBm Max (Si4432)



+13 dBm Max (Si4430/31)

Low Power Consumption



18.5 mA receive



30 mA @ +13 dBm transmit



85 mA @ +20 dBm transmit

Data Rate = 0.123 to 256 kbps

FSK, GFSK, and OOK modulation

Power Supply = 1.8 to 3.6 V

Ultra low power shutdown mode

Digital RSSI



Wake-up timer

Auto-frequency calibration (AFC)

Power-on-reset (POR)

Antenna diversity and TR switch

control

Configurable packet handler

Preamble detector

TX and RX 64 byte FIFOs

Low battery detector

Temperature sensor and 8-bit ADC

–40 to +85 °C temperature range

Integrated voltage regulators

Frequency hopping capability

On-chip crystal tuning

20-Pin QFN package

Low BOM

Ordering Information:

See page 67.

Pin Assignments

Si4430/31/32

XOUT

nSEL

15 SCLK

14 SDI

13 SDO

12 VDD_DIG

GPIO_0

GPIO_1

GPIO_2

10 11 NC

VR_DIG

nIRQ

SDN

XIN

Applications



Remote control

Home security & alarm

Telemetry

Personal data logging

Toy control

Tire pressure monitoring

Wireless PC peripherals



Remote meter reading

Remote keyless entry

Home automation

Industrial control

Sensor networks

Health monitors

Tag readers

VDD_RF 1

TX 2

RXp 3

RXn 4

NC 5

ANT

20 19 18 17 16

GND

PAD

Description

Silicon Laboratories’ Si4430/31/32 devices are highly integrated, single chip

wireless ISM transceivers. The high-performance EZRadioPRO

family includes

a complete line of transmitters, receivers, and transceivers allowing the RF

system designer to choose the optimal wireless part for their application.

The Si4430/31/32’s high level of integration offers reduced BOM cost while

simplifying the overall system design. The extremely low receive sensitivity

(–121 dBm) coupled with industry leading +20 dBm output power ensures

extended range and improved link performance. Built-in antenna diversity and

support for frequency hopping can be used to further extend range and enhance

performance.

The Si4430/31/32 offers advanced radio features including continuous frequency

coverage from 240–960 MHz in 156 Hz or 312 Hz steps allowing precise tuning

control. Additional system features such as an automatic wake-up timer, low

battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble

detection reduce overall current consumption and allow the use of lower-cost

system MCUs. An integrated temperature sensor, general purpose ADC, power-

on-reset (POR), and GPIOs further reduce overall system cost and size.

The Si4430/31/32’s digital receive architecture features a high-performance ADC

and DSP based modem which performs demodulation, filtering, and packet

handling for increased flexibility and performance. The direct digital transmit

modulation and automatic PA power ramping ensure precise transmit modulation

and reduced spectral spreading ensuring compliance with global regulations

including FCC, ETSI, ARIB, and 802.15.4d regulations.

An easy-to-use calculator is provided to quickly configure the radio settings,

simplifying customer's system design and reducing time to market.

Rev 1.1 10/10

Patents pending

Si4430/31/32

Si4430/31/32-B1

ABLE

Section

ONTENTS

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

5.7. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.8. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

5.9. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

6.4. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

6.5. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.6. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.7. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.8. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.9. Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.10. Receive Header Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.11. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Rev 1.1

Si4430/31/32-B1

8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

8.6. Wake-Up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.9. Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.10. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

10. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

12. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

13. Pin Descriptions: Si4430/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

15. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

15.1. Si4430/31/32 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

15.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

16. Package Outline: Si4430/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

17. PCB Land Pattern: Si4430/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Rev 1.1

Si4430/31/32-B1

IST

IGURES

Figure 1. Si4430/31 RX/TX Direct-Tie Application Example ..................................................... 16

Figure 2. Si4432 Antenna Diversity Application Example ......................................................... 16

Figure 3. SPI Timing.................................................................................................................. 18

Figure 4. SPI Timing—READ Mode ..........................................................................................19

Figure 5. SPI Timing—Burst Write Mode .................................................................................. 19

Figure 6. SPI Timing—Burst Read Mode .................................................................................. 19

Figure 7. State Machine Diagram.............................................................................................. 20

Figure 8. TX Timing................................................................................................................... 24

Figure 9. RX Timing .................................................................................................................. 24

Figure 10. Frequency Deviation ................................................................................................ 28

Figure 11. Sensitivity at 1% PER vs. Carrier Frequency Offset ................................................29

Figure 12. FSK vs GFSK Spectrums......................................................................................... 32

Figure 13. Direct Synchronous Mode Example......................................................................... 35

Figure 14. Direct Asynchronous Mode Example ....................................................................... 35

Figure 15. Microcontroller Connections..................................................................................... 36

Figure 16. PLL Synthesizer Block Diagram............................................................................... 38

Figure 17. FIFO Thresholds ...................................................................................................... 41

Figure 18. Packet Structure....................................................................................................... 42

Figure 19. Multiple Packets in TX Packet Handler .................................................................... 43

Figure 20. Required RX Packet Structure with Packet Handler Disabled ................................. 43

Figure 21. Multiple Packets in RX Packet Handler.................................................................... 43

Figure 22. Multiple Packets in RX with CRC or Header Error ................................................... 44

Figure 23. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 46

Figure 24. Manchester Coding Example ...................................................................................46

Figure 25. Header ..................................................................................................................... 48

Figure 26. POR Glitch Parameters............................................................................................ 50

Figure 27. General Purpose ADC Architecture ......................................................................... 52

Figure 28. Temperature Ranges using ADC8 ........................................................................... 54

Figure 29. WUT Interrupt and WUT Operation.......................................................................... 57

Figure 30. Low Duty Cycle Mode .............................................................................................. 58

Figure 31. RSSI Value vs. Input Power..................................................................................... 61

Figure 32. TX/RX Direct-Tie Reference Design—Schematic.................................................... 62

Figure 33. 20-Pin Quad Flat No-Lead (QFN) ............................................................................69

Figure 34. PCB Land Pattern .................................................................................................... 70

Rev 1.1

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