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DM74LS33M

Description
Quad 2-Input NOR Buffer with Open-Collector Outputs
Categorylogic    logic   
File Size42KB,4 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS33M Overview

Quad 2-Input NOR Buffer with Open-Collector Outputs

DM74LS33M Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codeunknow
seriesLS
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length8.65 mm
Logic integrated circuit typeNOR GATE
MaximumI(ol)0.024 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristicsOPEN-COLLECTOR
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)13.8 mA
Prop。Delay @ Nom-Su22 ns
propagation delay (tpd)22 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
DM74LS33 Quad 2-Input NOR Buffer with Open-Collector Outputs
March 1989
Revised March 2000
DM74LS33
Quad 2-Input NOR Buffer with Open-Collector Outputs
General Description
This device contains four independent gates each of which
perform the logic NOR function. Outputs are open-collec-
tor.
Ordering Code:
Order Number
DM74LS33M
DM74LS33N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y
=
A
+
B
Inputs
A
L
L
H
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
Output
B
L
H
L
H
Y
H
L
L
L
© 2000 Fairchild Semiconductor Corporation
DS010170
www.fairchildsemi.com

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