MT42L512M32D4GULH-3WT:A datasheet, PDF

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MT42L512M32D4GULH-3WT:A: DescriptionDDR DRAM; Categorystorage storage; File Size7MB，167 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT42L512M32D4GULH-3WT:A Overview

DDR DRAM

MT42L512M32D4GULH-3WT:A Parametric

Parameter Name	Attribute value
Maker	Micron Technology
package instruction	,
Reach Compliance Code	unknown
Memory IC Type	DDR DRAM
Base Number Matches	1

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4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Mobile LPDDR2 SDRAM

MT42L256M16D1, MT42L128M32D1, MT42L256M32D2,

MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,

MT42L256M64D4

Features

• Ultra low-voltage core and I/O power supplies

– V

DD2

= 1.14–1.30V

– V

DDCA

DDQ

= 1.14–1.30V

– V

DD1

= 1.70–1.95V

• Clock frequency range

– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)

• Four-bit prefetch DDR architecture

• Eight internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on every CK edge

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable READ and WRITE latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per-bank refresh for concurrent operation

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock stop capability

• RoHS-compliant, “green” packaging

Table 1: Key Timing Parameters

Speed Clock Rate Data Rate

Grade

(MHz)

(Mb/s/pin)

-18

-25

-3

533

400

333

1066

800

667

RCD/

Options

• V

DD2

: 1.2V

• Configuration

– 32 Meg x 16 x 8 banks x 1 die

– 16 Meg x 32 x 8 banks x 1 die

– 16 Meg x 32 x 8 banks x 2 die

– 32 Meg x 16 x 8 banks x 4 die

– 16 Meg x 32 x 8 banks x 2 die

– 16 Meg x 32 x 8 banks x 3 die

– 16 Meg x 32 x 8 banks x 4 die

• Device type

– LPDDR2-S4, 1 die in package

– LPDDR2-S4, 2 die in package

– LPDDR2-S4, 3 die in package

– LPDDR2-S4, 4 die in package

• FBGA “green” package

– 134-ball FBGA (10mm x

11.5mm)

– 168-ball FBGA (12mm x 12mm)

– 216-ball FBGA (12mm x 12mm)

– 220-ball FBGA (14mm x 14mm)

– 240-ball FBGA (14mm x 14mm)

– 253-ball FBGA (11mm x 11mm)

• Timing – cycle time

– 1.875ns @ RL = 8

– 2.5ns @ RL = 6

– 3.0ns @ RL = 5

• Operating temperature range

– From –30°C to +85°C

– From –40°C to +105°C

• Revision

Note:

Marking

256M16

128M32

256M32

512M32

128M64

192M64

256M64

GU, GV

LF, LG

LH, LK, LL, LM

LD, MP

EU, EV

-18

-25

-3

Typical

1. For Fast

RCD/

RP, contact factory.

PDF: 09005aef84427aab

4gb_mobile_lpddr2_s4_u80m.pdf - Rev. M 10/12 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Contents

General Description ....................................................................................................................................... 11

General Notes ............................................................................................................................................ 11

Specifications ........................................................................................................................................... 12

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 22

Ball Assignments and Descriptions ................................................................................................................. 34

Functional Description ................................................................................................................................... 43

Power-Up ....................................................................................................................................................... 44

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 46

Power-Off ....................................................................................................................................................... 46

Uncontrolled Power-Off .............................................................................................................................. 47

Mode Register Definition ................................................................................................................................ 47

Mode Register Assignments and Definitions ................................................................................................ 47

ACTIVATE Command ..................................................................................................................................... 58

8-Bank Device Operation ............................................................................................................................ 58

Read and Write Access Modes ......................................................................................................................... 59

Burst READ Command ................................................................................................................................... 59

READs Interrupted by a READ ..................................................................................................................... 66

Burst WRITE Command .................................................................................................................................. 66

WRITEs Interrupted by a WRITE ................................................................................................................. 69

BURST TERMINATE Command ...................................................................................................................... 69

Write Data Mask ............................................................................................................................................. 71

PRECHARGE Command ................................................................................................................................. 72

READ Burst Followed by PRECHARGE ......................................................................................................... 73

WRITE Burst Followed by PRECHARGE ....................................................................................................... 74

Auto Precharge ........................................................................................................................................... 75

READ Burst with Auto Precharge ................................................................................................................. 75

WRITE Burst with Auto Precharge ............................................................................................................... 76

REFRESH Command ...................................................................................................................................... 78

REFRESH Requirements ............................................................................................................................. 84

SELF REFRESH Operation ............................................................................................................................... 86

Partial-Array Self Refresh – Bank Masking .................................................................................................... 87

Partial-Array Self Refresh – Segment Masking .............................................................................................. 88

MODE REGISTER READ ................................................................................................................................. 89

Temperature Sensor ................................................................................................................................... 91

DQ Calibration ........................................................................................................................................... 93

MODE REGISTER WRITE Command ............................................................................................................... 95

MRW RESET Command .............................................................................................................................. 95

MRW ZQ Calibration Commands ................................................................................................................ 96

ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 98

Power-Down .................................................................................................................................................. 98

Deep Power-Down ........................................................................................................................................ 105

Input Clock Frequency Changes and Stop Events ............................................................................................ 106

Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 106

Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 107

NO OPERATION Command ........................................................................................................................... 107

Simplified Bus Interface State Diagram ....................................................................................................... 107

Truth Tables .................................................................................................................................................. 109

Electrical Specifications ................................................................................................................................. 117

Absolute Maximum Ratings ....................................................................................................................... 117

PDF: 09005aef84427aab

4gb_mobile_lpddr2_s4_u80m.pdf - Rev. M 10/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Input/Output Capacitance ......................................................................................................................... 117

Electrical Specifications – I

Specifications and Conditions ........................................................................... 118

AC and DC Operating Conditions ................................................................................................................... 121

AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 123

REF

Tolerances ......................................................................................................................................... 124

Input Signal .............................................................................................................................................. 125

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 127

Single-Ended Requirements for Differential Signals .................................................................................... 128

Differential Input Crosspoint Voltage ......................................................................................................... 130

Input Slew Rate ......................................................................................................................................... 131

Output Characteristics and Operating Conditions ........................................................................................... 131

Single-Ended Output Slew Rate .................................................................................................................. 132

Differential Output Slew Rate ..................................................................................................................... 133

HSUL_12 Driver Output Timing Reference Load ......................................................................................... 135

Output Driver Impedance .............................................................................................................................. 135

Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 136

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 137

Output Impedance Characteristics Without ZQ Calibration ......................................................................... 137

Clock Specification ........................................................................................................................................ 141

CK(abs),

CH(abs), and

CL(abs) ................................................................................................................ 142

Clock Period Jitter .......................................................................................................................................... 142

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 142

Cycle Time Derating for Core Timing Parameters ........................................................................................ 143

Clock Cycle Derating for Core Timing Parameters ....................................................................................... 143

Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 143

Clock Jitter Effects on READ Timing Parameters .......................................................................................... 143

Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 144

Refresh Requirements .................................................................................................................................... 145

AC Timing ..................................................................................................................................................... 146

CA and CS# Setup, Hold, and Derating ........................................................................................................... 152

Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 159

Revision History ............................................................................................................................................ 166

Rev. M – 10/12 ........................................................................................................................................... 166

Rev. L – 08/12 ............................................................................................................................................ 166

Rev. K – 07/12 ............................................................................................................................................ 166

Rev. J – 07/12 ............................................................................................................................................. 166

Rev. I – 05/12 ............................................................................................................................................. 166

Rev. H – 04/12 ............................................................................................................................................ 166

Rev. G – 04/12 ............................................................................................................................................ 166

Rev. F – 03/12 ............................................................................................................................................ 166

Rev. E – 02/12 ............................................................................................................................................ 166

Rev. D – 12/11 ............................................................................................................................................ 167

Rev. C – 12/11 ............................................................................................................................................ 167

Rev. B – 05/11 ............................................................................................................................................ 167

Rev. A – 02/11 ............................................................................................................................................ 167

PDF: 09005aef84427aab

4gb_mobile_lpddr2_s4_u80m.pdf - Rev. M 10/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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