ZL38004GGG2 datasheet, PDF - EEWORLD Datasheet

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ZL38004GGG2: DescriptionADPCM Codec, 1-Func, PBGA96, 7 X 7 MM, 0.91 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, VFBGA-96; CategoryWireless rf/communication Telecom circuit; File Size128KB，8 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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ZL38004GGG2 Overview

ADPCM Codec, 1-Func, PBGA96, 7 X 7 MM, 0.91 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, VFBGA-96

ZL38004GGG2 Parametric

Parameter Name	Attribute value
Maker	Zarlink Semiconductor (Microsemi)
package instruction	TFBGA,
Reach Compliance Code	unknown
filter	YES
JESD-30 code	S-PBGA-B96
JESD-609 code	e3
length	7 mm
Number of functions	1
Number of terminals	96
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.01 mm
Nominal supply voltage	1.2 V
surface mount	YES
Telecom integrated circuit types	ADPCM CODEC
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
width	7 mm
Base Number Matches	1

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ZL38004

Dedicated Voice Processor

with Dual Channel Codec

Data Sheet

A full Design Manual is available to qualified

customers. To register, please send an email to

VoiceProcessing@Zarlink.com.

August 2011

Ordering Information

ZL38004QCG1

100 Pin LQFP*

96 Pin VFBGA*

*Pb Free Matte Tin

40C to +85C

Trays, Bake &

Drypack

Trays, Bake &

Drypack

Features

•

100 MHz (200 MIPs) Zarlink voice processor with

Butterfly hardware accelerator and

breakpoint/interrupt controller

On-board Data (26 Kbytes), Instruction (24

Kbytes RAM and Boot (3 Kbytes) ROM

Dual



ADCs with input buffer gain selection

programmable to either 8 or 16 kHz sampling

Dual

DACs

with output sampling of 8, 16, 44.1

and 48 kHz and internal output driver

2048 tap Filter co-processor shared across up to

16 separate functions in 128 tap increments

Dual function Inter-IC Sound (I

S) or Secondary

TDM port

Primary PCM port supports TDM (ST BUS, GCI or

McBSP framing) or SSI modes at bit rates of 128,

256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec

Separate slave (microcontroller) and master

(Flash) SPI ports, maximum clock rate = 25 MHz

•

ZL38004GGG2

•

Watchdog and 2 auxiliary timers

11 General Purpose Input/Output (GPIO) pins

General purpose UART port

Bootloadable for future Zarlink software upgrades

External oscillator or crystal/ceramic resonator

1.2 V Core; 3.3 V IO with 5 V-tolerant inputs

IEEE-1149.1 compatible JTAG port

Applications

•

Hands-free car kits

Full duplex speaker-phone for digital telephone

Echo cancellation for video conferences

•

Buffer

CODEC[0]

ADC

DAC

Driver

Buffer

ADC

DAC

Driver

IRQ

IRQ[15:0]

100 MHz MCLK

OSCo

APLL

Interrupt

Controller

DSP

Core

Instruction

RAM

24K

Bytes

Data RAM

Boot

ROM

PCM P0

Clock

Chain

OSC

OSCi

PCM_CLKi

PCM_LBCi

JTAG

CODEC[1]

Timing

Generator

IRQ

CODEC[1:0]

Device Clocks

ButterFly

Hardware

Accelerator

27K

Bytes

IRQ

Master

SPI

IRQ

PCM P0

IRQ

Slave

SPI

IRQ

APLL

MCLK

Watchdog

AUX Timer1

AUX Timer2

IRQ

UART

GPIO

I S

PCM P1

Filter

Co-processor

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL38004

2.0

Core DSP Functional Block

Data Sheet

The ZL38004 DSP Core functional block, illustrated in Figure 1, is made up of a DSP Core, Interrupt Controller,

Data RAM, Instruction RAM, BOOT ROM and a ButterFly Hardware Accelerator. This block controls the timing

(APLL and Timing Generator), peripheral interfaces and Filter Co-processor through a peripheral

address/data/control bus and 16 prioritized interrupts.

The ZL38004 implementation of DSP core and Filter Co-processor have been optimized to efficiently support voice

processing applications. These applications are described in detail in the firmware manuals associated with this

hardware platform.

When an interrupt occurs the DSP core saves its current status and jumps to the address of the associated interrupt

service routine.

3.0

Codec[1:0]

The ZL38004 has two 16-bit fully differential



CODECs (CODEC 0/1) that can be programmed for 48 kHz or

44.1 kHz sampling, or to meet G.712 requirements at 8 kHz sampling or G.722 at 16 kHz sampling, see Figure 2.

The ADC path consists of input signal pins C0/1_ADCi+ and C0/1_ADCi- (buffer output pins C0/1_BF0+ and

C0/1_BFo-), which feed selectable Microphone Amplifier or Line Amplifier options. Once past the buffer the analog

signal goes through a low pass antialiasing filter and to a 4

order feed-forward



Modulator that produces a

Pulse Density Modulated (PDM) signal. Next the PDM signal goes through a Low Pass Decimation Filter and then

is converted into a 16-bit parallel word that can be read by the ZL38004 DSP (ADCout[15:0], Figures 2).

The ZL38004 DSP will send 16-bit parallel word samples (DACin[15:0], Figure 2) to the DAC where they are

converted to serial data and passed through an interpolation filter followed by a digital



Modulator. The



Modulator generates PDM data, which then passes through a 32-tap FIR reconstruction filter. The reconstructed

analog signal is then passed to a unity voltage gain differential output driver and to pins C0/1_DACo+ and

C0/1_DACo-.

The CODEC bias voltages are generated by an internal bandgap circuit (BIAS_VCM, BIAS_RF+ and BIAS_RF-).

Each ZL38004 CODEC has two loopbacks. When activated, the input analog signal on pins C0/1_ADC+/- is looped

around to C0/1_DAC+/-. Pulse Density Modulated (PDM) serial data from the ADC Analog



Modulator output is

looped around to the input of the DAC Reconstruction Filter. At the same time 16-bit parallel data is looped around

from DACin[15:0] to ADCout[15:0]. PDM serial data from the DAC Digital



Modulator is looped around to the

input of the ADC Digital Low Pass Decimation Filter.

When the Parallel Loopback is activated the input analog signal on pins C0/1_ADC+/- is looped around to the

C0/1_DAC+/- output. 16-bit parallel data from the ADC Digital Low Pass Decimation Filter is looped around to the

DAC Digital Low Pass Interpolation Filter. This data may be read by the DSP, but parallel data written to the DAC by

the DSP will be lost.

CODEC0 and CODCE1 of the ZL38004 may be powered down if they are not required. See firmware manual.

Zarlink Semiconductor Inc.

ZL38004

5.0

Host Microprocessor and Peripheral Interfaces

Data Sheet

The ZL38004 provides 1 master SPI port (with 2 chip selects), 1 slave SPI ports and an UART. The master SPI

port’s primary function is to access and external FLASH memory to download firmware to the ZL38004.

The control/status registers and memory of the ZL38004 can be accessed (R/W) by an external host through the

Slave SPI and the UART ports. Register/Memory read and write accesses are carried out through a series of port

read and write accesses as follows:

5.1

Master SPI (FLASH Port)

The Master SPI port is used by the ZL38004 to access one or two peripheral devices (chip select signals

SPIM_CS[1:0]). It supports both SPI and MICROWIRE modes of operation and can write up to 40 bits or read up to

32 bits in a single access. The Chip Select output signals may be programmed for a single access or burst access.

All communication is MSB first and all pins of the master SPI port are outputs controlled by the ZL38004, except

SPIM_MISO.

5.2

Slave SPI (Host Port)

The slave SPI port may be used by an external host microprocessor to access (Read/Write) the ZL38004 internal

control/status registers and memory. Access is initiated when the external host makes signal SPIS_CS low and is

ended when this signal goes high. The host will then apply a clock (maximum 25 MHz) to signal SPIS_CLK to clock

data out of SPIS_MISO and in on SPIS_MOSI.

5.3

UART

The UART (Universal Asynchronous Receiver Transmitter) port may be used by an external host microprocessor to

access (Read/Write) the ZL38004 internal control/status registers and memory. The ZL38004 DSP will set up the

initial parameters of this port (i.e., master/slave, baud rate, stop bits, parity bit...) during the Boot process. After the

device has been booted these port options can be changed as per the firmware manual.

The UART port will support 8-bit data only with any combination of 1 start bit, 0 or 1 parity bit(s) and 1, 1.5 or 2 stop

bit(s).

The ZL38004 has 11 GPIO (General Purpose Input/Output) pins that can be individually configured as either input

or output. These pins are intended for low frequency signalling.

When a GPIO pin is defined as an input the state of that input pin is sampled with the internal master clock (Mclk =

100 MHz) and latched into the GPIO Read Register. This sampling can be stopped (Freeze) on an individual GPIO

pin. Individual pins of GPIO[4:0] may have an internal pull-down resistor activated/deactivated and individual pins of

GPIO[10:5] may have an internal pull-up activated/deactivated.

Immediately after a power-on reset (RST pin) the GPIO pins are defined as inputs and their state is captured in the

GPIO Start-Up Status Register. The state of this register is used by the Boot program to determine the base

functionality and programming options of the device.

Individual GPIO pins may also be defined as outputs with associated enable/disable (active/high impedance)

control.

Zarlink Semiconductor Inc.

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