RELEASED
DATASHEET
PMC-2010336
ISSUE 1
PM7383 FREEDM-32A256
FRAME ENGINE AND DATA LINK MANAGER 32A256
PM7383
FREEDM™-32A256
FRAME ENGINE AND DATALINK
MANAGER 32A256
DATASHEET
PROPRIETARY AND CONFIDENTIAL
RELEASED
ISSUE 2: AUGUST 2001
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
RELEASED
DATASHEET
PMC-2010336
ISSUE 1
PM7383 FREEDM-32A256
FRAME ENGINE AND DATA LINK MANAGER 32A256
CONTENTS
1
2
3
4
5
6
7
8
FEATURES...............................................................................................1
APPLICATIONS ........................................................................................4
REFERENCES .........................................................................................5
BLOCK DIAGRAM....................................................................................6
DESCRIPTION .........................................................................................7
PIN DIAGRAM ........................................................................................ 11
PIN DESCRIPTION ................................................................................12
FUNCTIONAL DESCRIPTION................................................................44
8.1
8.2
8.3
HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL
(H-MVIP) ......................................................................................44
HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........44
RECEIVE CHANNEL ASSIGNER ................................................45
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
Line Interface Translator (LIT) .......................................47
Line Interface .................................................................48
Priority Encoder .............................................................48
Channel Assigner ..........................................................49
Loopback Controller.......................................................49
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER ...49
8.4.1
8.4.2
HDLC Processor............................................................50
Partial Packet Buffer Processor .....................................50
8.5
RECEIVE ANY-PHY INTERFACE ................................................52
8.5.1
FIFO Storage and Control..............................................53
PROPRIETARY AND CONFIDENTIAL
i
RELEASED
DATASHEET
PMC-2010336
ISSUE 1
PM7383 FREEDM-32A256
FRAME ENGINE AND DATA LINK MANAGER 32A256
8.5.2
8.6
Polling Control and Management...................................54
TRANSMIT ANY-PHY INTERFACE .............................................54
8.6.1
8.6.2
FIFO Storage and Control..............................................54
Polling Control and Management...................................56
8.7
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER57
8.7.1
8.7.2
Transmit HDLC Processor .............................................57
Transmit Partial Packet Buffer Processor ......................58
8.8
TRANSMIT CHANNEL ASSIGNER..............................................60
8.8.1
8.8.2
8.8.3
8.8.4
Line Interface Translator (LIT) .......................................62
Line Interface .................................................................63
Priority Encoder .............................................................63
Channel Assigner ..........................................................64
8.9
8.10
8.11
9
PERFORMANCE MONITOR .......................................................64
JTAG TEST ACCESS PORT INTERFACE...................................64
MICROPROCESSOR INTERFACE .............................................64
NORMAL MODE REGISTER DESCRIPTION ........................................68
9.1
MICROPROCESSOR ACCESSIBLE REGISTERS .....................68
10
TEST FEATURES DESCRIPTION .......................................................159
10.1
10.2
TEST MODE REGISTERS.........................................................159
JTAG TEST PORT .....................................................................160
10.2.1
10.2.2
Identification Register ..................................................161
Boundary Scan Register ..............................................161
11
OPERATIONS.......................................................................................180
11.1
TOCTL CONNECTIONS ............................................................180
PROPRIETARY AND CONFIDENTIAL
ii
RELEASED
DATASHEET
PMC-2010336
ISSUE 1
PM7383 FREEDM-32A256
FRAME ENGINE AND DATA LINK MANAGER 32A256
11.2
12
JTAG SUPPORT........................................................................180
FUNCTIONAL TIMING..........................................................................187
12.1
12.2
12.3
12.4
12.5
12.6
12.7
RECEIVE H-MVIP LINK TIMING ...............................................187
TRANSMIT H-MVIP LINK TIMING .............................................188
RECEIVE NON H-MVIP LINK TIMING.......................................190
TRANSMIT NON H-MVIP LINK TIMING ....................................191
RECEIVE APPI TIMING .............................................................193
TRANSMIT APPI TIMING ..........................................................197
BERT INTERFACE.....................................................................200
13
14
15
16
17
ABSOLUTE MAXIMUM RATINGS........................................................202
D.C. CHARACTERISTICS....................................................................203
FREEDM-32A256 TIMING CHARACTERISTICS .................................206
ORDERING AND THERMAL INFORMATION ......................................220
MECHANICAL INFORMATION.............................................................221
PROPRIETARY AND CONFIDENTIAL
iii
RELEASED
DATASHEET
PMC-2010336
ISSUE 1
PM7383 FREEDM-32A256
FRAME ENGINE AND DATA LINK MANAGER 32A256
LIST OF FIGURES
FIGURE 1 – H-MVIP PROTOCOL.....................................................................44
FIGURE 2 – HDLC FRAME...............................................................................45
FIGURE 3 – CRC GENERATOR.......................................................................45
FIGURE 4 – PARTIAL PACKET BUFFER STRUCTURE ..................................51
FIGURE 5 – PARTIAL PACKET BUFFER STRUCTURE ..................................58
FIGURE 6 – INPUT OBSERVATION CELL (IN_CELL) ...................................176
FIGURE 7 – OUTPUT CELL (OUT_CELL)......................................................177
FIGURE 8 – BI-DIRECTIONAL CELL (IO_CELL)............................................178
FIGURE 9 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS179
FIGURE 10 – BOUNDARY SCAN ARCHITECTURE ......................................181
FIGURE 11 – TAP CONTROLLER FINITE STATE MACHINE.........................183
FIGURE 12 – RECEIVE 8.192 MBPS H-MVIP LINK TIMING .........................187
FIGURE 13 – RECEIVE 2.048 MBPS H-MVIP LINK TIMING .........................188
FIGURE 14 – TRANSMIT 8.192 MBPS H-MVIP LINK TIMING .......................189
FIGURE 15 – TRANSMIT 2.048 MBPS H-MVIP LINK TIMING .......................189
FIGURE 16 – UNCHANNELISED RECEIVE LINK TIMING ............................190
FIGURE 17 – CHANNELISED T1/J1 RECEIVE LINK TIMING........................191
FIGURE 18 – CHANNELISED E1 RECEIVE LINK TIMING ............................191
FIGURE 19 – UNCHANNELISED TRANSMIT LINK TIMING ..........................192
FIGURE 20 – CHANNELISED T1/J1 TRANSMIT LINK TIMING .....................192
FIGURE 21 – CHANNELISED E1 TRANSMIT LINK TIMING..........................193
FIGURE 22 – RECEIVE APPI TIMING (NORMAL TRANSFER) .....................193
PROPRIETARY AND CONFIDENTIAL
iv
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