TECHNICAL DATA
IW4034B
8-Stage Static Bidirectional Parallel/
Serial Input/Output Bus Register
High-Voltage Silicon-Gate CMOS
The IW4034B is a static eight-stage parallel-or serial-input parallel-
output register. It can be used to:
1) bidirectionally transfer parallel information between two buses, 2)
convert serial data to parallel form and direct the parallel data to either of
two buses, 3) store (recirculate) parallel data, or 4) accept parallel data
from either of two buses and convert that data to serial form. Inputs that
control the operations include a single-phase CLOCK (CL), A DATA
ORDERING INFORMATION
ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-
IW4034BN Plastic
TO-B-BUS/ B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S).
IW4034BDW SOIC
Data inputs include 16 bidirectional parallel data lines of which the
T
A
= -55° to 125° C for all packages
eight A data lines are inputs (3-state outputs) and the B data lines are
outputs (inputs) dependung on the signal level on the A/B input. In
addition, an input for SERIAL DATA is also provided.
All register stages are D-type master-slave flip-flops with separate
master and slave clock inputs generated internally to allow synchronous
or asynchronous data transfer from master to slave.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
μA
at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 24=V
CC
PIN 12= GND
1
IW4034B
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
3.0
0
-55
Max
18
V
CC
+125
Unit
V
V
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
IW4034B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
Parameter
Minimum High-Level
Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
Leakage Current
Minimum Three State
Leakage Current
Test Conditions
V
OUT
= 0.5 V or V
CC
- 0.5V
V
OUT
= 1.0 V or V
CC
- 1.0 V
V
OUT
= 1.5 V V
CC
- 1.5V
V
OUT
= 0.5 V or V
CC
- 0.5V
V
OUT
= 1.0 V or V
CC
- 1.0 V
V
OUT
= 1.5 V V
CC
- 1.5V
V
IN
=GND or V
CC
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
18
18
Guaranteed Limit
≥-55°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
±0.4
25°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
±0.4
≤125
°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±1.0
±12.0
Unit
V
V
IL
V
V
OH
V
V
OL
V
IN
=GND or V
CC
V
I
IN
I
OZ
V
IN
= GND or V
CC
Output in High-Impedance
State
V
IN
= GND or V
CC
V
OUT
= GND or V
CC
V
IN
= GND or V
CC
μA
μA
I
CC
Maximum Quiescent
Supply Current
(per Package)
Minimum Output
Low (Sink) Current
5.0
10
15
20
5.0
10
15
5.0
5.0
10
15
5
10
20
100
0.64
1.6
4.2
-2
-0.64
-1.6
-4.2
5
10
20
100
0.51
1.3
3.4
-1.6
-0.51
-1.3
-3.4
150
300
600
3000
0.36
0.9
2.4
μA
I
OL
V
IN
= GND or V
CC
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
mA
I
OH
Minimum Output
V
IN
= GND or V
CC
High (Source) Current U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
mA
-1.15
-0.36
-0.9
-2.4
3
IW4034B
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (Figure 2)
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
-
2
5
7
700
240
170
400
160
120
200
100
80
Guaranteed Limit
≥-55°C
25°C
2
5
7
700
240
170
400
160
120
200
100
80
7.5
≤125°C
1
2.5
3.5
1400
480
340
800
320
240
400
200
160
Unit
MHz
t
PHL
, t
PLH
Maximum Propagation Delay, A(B) Parallel
Data In to B(A) Parallel Data Out; Serial to
Parallel Data Out (Figures 1,2)
Maximum Propagation Delay, A/B or AE to
“A” Output (Figure 3)
Maximum Output Transition Time, Any Output
(Figures 1,2)
Maximum Input Capacitance
ns
t
PLZ
, t
PHZ,
t
PZL
, t
PZH
t
THL
, t
TLH
ns
ns
C
IN
pF
TIMING REQUIREMENTS
(C
L
=50pF, R
L
=200 kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, Serial Data to Clock
(Figure 4)
Minimum Setup Time, Parallel Data to Clock
(Figure 4)
Minimum Hold Time, Clock to Data (Figure 4)
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
160
60
40
50
30
20
50
15
10
350
140
80
250
100
70
15
15
15
Guaranteed Limit
≥-55°C
25°C
160
60
40
50
30
20
50
15
10
350
140
80
250
100
70
15
15
15
≤125°C
320
120
80
100
60
40
100
30
20
700
280
160
500
200
140
30
30
30
Unit
ns
t
su
ns
t
h
ns
t
w
Minimum Pulse Width, AE, P/S, A/S
(Figure 5)
Minimum Pulse Width, Clock (Figure 2)
ns
t
w
ns
t
r
,t
f
Minimum Input Rise or Fall Time, Clock
(Figure 2)
ns
4
IW4034B
TRUTH TABLE FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER
OPERATION
“A”
Enable
L
L
L
L
L
L
H
H
H
H
H
H
P/S
L
L
H
H
H
H
L
L
H
H
H
H
A/B
L
H
L
L
H
H
L
H
L
L
H
A/S
X
X
L
H
L
H
X
X
L
H
L
Operation
*
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled
Serial Mode, Synch. Serial Data Input, “B” Parallel Data Output
Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs
Disabled
Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs
Disabled
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs,
Synch. Data Recirculation
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs,
Asynch. Data Recirculation
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output
Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output
Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output
Parallel Mode; “A” Synch. Parallel Data Input, “B” Parallel Data Output
H
H Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output
*
Outputs change at positive transition of clock in the serial mode and when the A/S control input is “low” in the
parallel mode. During transfer from parallel to serial operation A/S should remain low in oder to prevent D
S
transfer
into Flip Flops.
X = Don’t Care
PARALLEL OPERATION
A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the
positive transition of the clock provided the A/S input is low. If the A/S input is high the transfer is independent of the
clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs
(and B data lines are outputs); a low A/B signal reverses the direction of data flow.
The AE input is an additional feature which allows many registers to feed data to a common bus. The A DATA
lines are enabled only when this signal is high.
Data storage through recirculation of data in each register stage is accomplished by making the A/B signal high
and the AE signal low.
SERIAL OPERATION
A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of the
clock. The A/S input is internally disabled when the register is in the serial mode (asynchronous serial operation is not
allowed).
The serial data appears as output data on either the B lines (when A/B is high) or the A lines (when A/B is low
and the AE signal is high).
5
Analog electronics
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