P5C032-40 datasheet, PDF - EEWORLD Datasheet

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P5C032-40: Description8-MACROCELL CMOS PLD; CategoryProgrammable logic devices Programmable logic; File Size678KB，13 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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P5C032-40 Overview

8-MACROCELL CMOS PLD

P5C032-40 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	DIP
package instruction	DIP, DIP20,.3
Contacts	20
Reach Compliance Code	unknow
Other features	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	18.5 MHz
JESD-30 code	R-PDIP-T20
JESD-609 code	e0
length	25.55 mm
Dedicated input times	8
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	72
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	OT PLD
propagation delay	40 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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P5C032-40 Related Products

	P5C032-40	5C032	D5C032-30	D5C032-35	P5C032-30	TP5C032-35	D5C032-40	P5C032-35
Description	8-MACROCELL CMOS PLD	8-MACROCELL CMOS PLD	8-MACROCELL CMOS PLD	8-MACROCELL CMOS PLD	8-MACROCELL CMOS PLD	8-MACROCELL CMOS PLD	8-MACROCELL CMOS PLD	8-MACROCELL CMOS PLD
Is it Rohs certified?	incompatible	-	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Intel	-	Intel	Intel	Intel	Intel	Intel	Intel
Parts packaging code	DIP	-	DIP	DIP	DIP	-	DIP	DIP
package instruction	DIP, DIP20,.3	-	DIP, DIP20,.3	DIP, DIP20,.3	DIP, DIP20,.3	DIP, DIP20,.3	DIP, DIP20,.3	DIP, DIP20,.3
Contacts	20	-	20	20	20	-	20	20
Reach Compliance Code	unknow	-	compli	compli	compli	compli	compli	unknow
Other features	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	-	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	-	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE	-	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE
maximum clock frequency	18.5 MHz	-	25 MHz	22.2 MHz	25 MHz	25 MHz	18.5 MHz	22.2 MHz
JESD-30 code	R-PDIP-T20	-	R-GDIP-T20	R-GDIP-T20	R-PDIP-T20	R-PDIP-T20	R-GDIP-T20	R-PDIP-T20
JESD-609 code	e0	-	e0	e0	e0	e0	e0	e0
length	25.55 mm	-	24.825 mm	24.825 mm	25.55 mm	-	24.825 mm	25.55 mm
Dedicated input times	8	-	8	8	8	-	8	8
Number of I/O lines	8	-	8	8	8	-	8	8
Number of entries	18	-	18	18	18	18	18	18
Output times	8	-	8	8	8	8	8	8
Number of product terms	72	-	72	72	72	72	72	72
Number of terminals	20	-	20	20	20	20	20	20
Maximum operating temperature	70 °C	-	70 °C	70 °C	70 °C	85 °C	70 °C	70 °C
organize	8 DEDICATED INPUTS, 8 I/O	-	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	-	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	-	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	-	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY
encapsulated code	DIP	-	DIP	DIP	DIP	DIP	DIP	DIP
Encapsulate equivalent code	DIP20,.3	-	DIP20,.3	DIP20,.3	DIP20,.3	DIP20,.3	DIP20,.3	DIP20,.3
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	-	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	-	5 V	5 V	5 V	5 V	5 V	5 V
Programmable logic type	OT PLD	-	UV PLD	UV PLD	OT PLD	-	UV PLD	OT PLD
propagation delay	40 ns	-	30 ns	35 ns	30 ns	35 ns	40 ns	35 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	-	5.08 mm	5.08 mm	5.08 mm	-	5.08 mm	5.08 mm
Maximum supply voltage	5.25 V	-	5.25 V	5.25 V	5.25 V	-	5.25 V	5.25 V
Minimum supply voltage	4.75 V	-	4.75 V	4.75 V	4.75 V	-	4.75 V	4.75 V
Nominal supply voltage	5 V	-	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	-	NO	NO	NO	NO	NO	NO
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	-	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	-	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	-	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	-	7.62 mm	7.62 mm	7.62 mm	-	7.62 mm	7.62 mm

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