SL4081B
Quad 2-Input AND Gate
High-Voltage Silicon-Gate CMOS
The SL4081B AND gates provide the system designer with direct
emplementation of the AND function.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4081BN Plastic
SL4081BD SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
PIN 14 =V
CC
PIN 7 = GND
A
L
L
H
H
B
L
H
L
H
Output
Y
L
L
L
H
SLS
System Logic
Semiconductor
SL4081B
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
3.0
0
-55
Max
18
V
CC
+125
Unit
V
V
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL4081B
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A or B to
Output Y (Figure 1)
Maximum Output Transition Time, Any Output
(Figure 1)
Maximum Input Capacitance
V
5.0
10
15
5.0
10
15
-
Guaranteed Limit
≥-55°C
250
120
90
200
100
80
25°C
250
120
90
200
100
80
7.5
≤125°C
500
240
180
400
200
160
Unit
ns
t
TLH
, t
THL
ns
C
IN
pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
SLS
System Logic
Semiconductor
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