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EM421M1684RTA-75FE

Description
512mb (8M?—4bank?—16) double data rate sdram
File Size281KB,19 Pages
ManufacturerEOREX
Websitehttp://www.eorex.com
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EM421M1684RTA-75FE Overview

512mb (8M?—4bank?—16) double data rate sdram

eorex
Features
• Internal Double-Date-Rate architecture with 2
Accesses per clock cycle.
• Single 2.5V
±0.2V
Power Supply
• 2.5V SSTL-2 compatible I/O
• Burst Length (B/L) of 2, 4, 8
• 2,2.5,3 Clock read latency
• Bi-directional,intermittent data strobe(DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• DLL aligns DQ & DQS transitions with CLK
transition
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
EM42BM1684RTA
512Mb (8M
×
4Bank
×
16)
Double DATA RATE SDRAM
Description
The EM42BM1684RTA is high speed Synchronous
graphic RAM fabricated with ultra high performance
CMOS process containing 536,870,912 bits which
organized as 8Meg words x 4 banks by 16 bits.
The 512Mb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation.
The data path internally prefetches multiple bits and
It transfers the datafor both rising and falling edges
of the system clock.It means the doubled data
bandwidth can be achieved at the I/O pins.
Available packages:TSOPII 66P 400mil.
Ordering Information
Part No
EM42BM1684RTA-75F
EM42BM1684RTA-6F
EM42BM1684RTA-5F
Organization
32M X 16
32M X 16
32M X 16
Max. Freq
133MHz @CL25
166MHz @CL25
200MHz @CL3
Package
66pin TSOP(ll)
66pin TSOP(ll)
66pin TSOP(ll)
Grade
Commercial
Commercial
Commercial
Pb
Free
Free
Free
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
1/19
www.eorex.com

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