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PI2EQX5864DZFEX

Description
Buffers u0026 Line Drivers 5.0Gbps 4ln PCIe2.0 Redrivr w/I2C config
Categorysemiconductor    logic   
File Size1MB,23 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
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PI2EQX5864DZFEX Overview

Buffers u0026 Line Drivers 5.0Gbps 4ln PCIe2.0 Redrivr w/I2C config

PI2EQX5864DZFEX Parametric

Parameter NameAttribute value
Product CategoryBuffers & Line Drivers
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
RoHSDetails
PackagingReel
Factory Pack Quantity2000
PI2EQX5864D
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization, Emphasis, & I
2
C Control
Features
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Description
Pericom Semiconductor’s PI2EQX5864D is a low power, PCIe
®
compliant signal redriver. The device provides programmable
equalization, amplification, and de-emphasis by using 8 select
bits, to optimize performance over a variety of physical mediums
by reducing Inter-symbol interference.
PI2EQX5864D supports eight 100-Ohm Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI Express signal before the ReDriver™,
whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the signal after the redriver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5864D also provides power management Stand-by mode
operated by a Bus Enable pin.
Up to 5.0Gbps PCI Express
®
2.0 Serial ReDriver
Supporting 8 differential channels or 4 lanes of PCIe
Interface
Adjustable receiver equalization and transmitter de-
emphasis and output levels
Variable input an output termination
1:2 channel broadcast
Channel loop-back
Electrical Idle fully supported
Receiver detect and individual output control
Single supply voltage, 1.2V ± 0.05V
Power down modes
Packaging: 56-contact TQFN, Pb-free & Green
Î
I
2
C configuration controls (3.3V tolerant)
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Block Diagram
+
xyRx+
xyRx-
+
Input½level½detect
to½control½logic
Output
Controls
+
xxTx+
xxTx-
Pin Configuration
SDA
NC
RXD_A
GND
GND
NC
VDD
SCL
Equalizer
A
B
Input½level½detect
to½control½logic
+
VDD
A0RX+
A0RX-
B0TX+
B0TX-
VDD
A1RX+
A1RX-
B1TX-
B1TX+
VDD
A2RX+
A2RX-
B2TX-
B2TX+
VDD
A3RX+
A3RX-
B3TX+
B3TX-
xyTx+
xyTx-
+
Output
Controls
Equalizer
+
56 55 54
53
52 51 50 49
1
48
2
47
3
46
4
45
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
A0TX+
A0TX-
B0RX+
B0RX-
VDD
A1TX+
A1TX-
B1RX-
B1RX+
VDD
A2TX+
A2TX-
B2RX-
B2RX+
VDD
A3TX+
A3TX-
B3RX+
B3RX-
VDD
xyRx+
xyRx-
Data½Lane½Repeats½4½Times
Control½registers
&½logic
Power
Management
SDA
SCL
Mode
LB#
RXD_x
RES_x
29
21 22 23
24
25 26 27 28
VDD
RXD_B
MODE
RESET#
A0
A1
LB#
A4
I
2
C½Control
Ax
All trademarks are property of their respective owners.
10-0172
1
www.pericom.com
PS 0.1
06/04/10
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