MC100LVEP14
2.5V / 3.3V 1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100LVEP14 is a low skew 1−to−5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single−ended (if the V
BB
output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The LVEP14 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50
W
even if only one output is being used. If an output pair is unused, both
outputs may be left open (unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock; therefore, all associated specification limits are referenced to
the negative edge of the clock input.
The MC100LVEP14, as with most other ECL devices, can be
operated from a positive V
CC
supply in PECL mode. This allows the
LVEP14 to be used for high performance clock distribution in +3.3 V
or +2.5 V systems. Single−ended CLK input pin operation is limited to
a V
CC
≥
3.0 V in PECL mode, or V
EE
≤
−3.0 V in NECL mode.
Designers can take advantage of the LVEP14’s performance to
distribute low skew clocks across the backplane or the board.
Features
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TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
20
100
VP14
ALYWG
G
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
100 ps Device−to−Device Skew
25 ps Within Device Skew
400 ps Typical Propagation Delay
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
PECL and HSTL Mode:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
•
NECL Mode:
V
CC
= 0 V with V
EE
= −2.375 V to −3.8 V
•
LVDS Input Compatible
•
Open Input Default State
•
These Devices are Pb−Free and are RoHS Compliant
©
Semiconductor Components Industries, LLC, 2014
1
April, 2014 − Rev. 14
Publication Order Number:
MC100LVEP14/D
MC100LVEP14
V
CC
20
EN
19
V
CC
18
CLK1
17
CLK1
16
V
BB
15
CLK0
14
CLK0 CLK_SEL V
EE
13
12
11
1
0
D
Q
1
Q0
2
Q0
3
Q1
4
Q1
5
Q2
6
Q2
7
Q3
8
Q3
9
Q4
10
Q4
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20−Lead Pinout
(Top View)
and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
CLK0*,
CLK0**
CLK1*,
CLK1**
Q0:4, Q0:4
CLK_SEL*
EN*
V
BB
V
CC
V
EE
Type
LVECL/LVPECL/
HSTL
LVECL/LVPECL/
HSTL
LVECL/LVPECL
LVECL/LVPECL
LVECL/LVPECL
LVECL/LVPECL
Function
ECL/PECL/HSTL CLK Input
ECL/PECL/HSTL CLK Input
ECL/PECL Outputs
ECL/PECL Active Clock Se-
lect Input
ECL Sync Enable
Reference Voltage Output
Positive Supply
Negative Supply
Table 2. FUNCTION TABLE
CLK0
L
H
X
X
X
CLK1
X
X
L
H
X
CLK_SEL
L
L
H
H
X
EN
L
L
L
L
H
Q
L
H
L
H
L*
*On next negative transition of CLK0 or CLK1
* Pins will default low when left open.
**Pins will default to V
CC
/2 when left open.
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
Level 1
Value
75 kW
37.5 kW
> 2 kV
> 100 V
> 2 kV
Pb−Free Pkg
Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−20
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
357 Devices
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2
MC100LVEP14
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
TSSOP−20
TSSOP−20
TSSOP−20
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
6
−6
6
−6
50
100
±
0.5
−40 to +85
−65 to +150
140
100
23 to 41
265
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. 100LVEP DC CHARACTERISTICS, PECL
V
CC
= 2.5 V, V
EE
= 0 V (Note 2)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended) (Note 4)
Input LOW Voltage (Single−Ended) (Note 4)
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
Input HIGH Current
Input LOW Current
CLK
CLK
0.5
−150
Min
45
1355
505
1335
505
1.2
Typ
60
1480
730
Max
75
1605
900
1620
900
2.5
150
0.5
−150
Min
45
1355
505
1335
505
1.2
25°C
Typ
60
1480
730
Max
75
1605
900
1620
900
2.5
150
0.5
−150
Min
45
1355
505
1275
505
1.2
85°C
Typ
60
1480
730
Max
75
1605
900
1620
900
2.5
150
Unit
mA
mV
mV
mV
mV
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to −1.3 V.
3. All loading with 50
W
to V
CC
− 2.0 V.
4. Do not use V
BB
at V
CC
< 3.0 V.
5. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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MC100LVEP14
Table 6. 100LVEP DC CHARACTERISTICS, PECL
V
CC
= 3.3 V, V
EE
= 0 V (Note 6)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Reference Voltage (Note 8)
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
Input HIGH Current
Input LOW Current
CLK
CLK
0.5
−150
Min
45
2155
1305
2135
1305
1775
1.2
1875
Typ
60
2280
1530
Max
75
2405
1700
2420
1700
1975
3.3
Min
45
2155
1305
2135
1305
1775
1.2
1875
25°C
Typ
60
2280
1530
Max
75
2405
1700
2420
1700
1975
3.3
Min
45
2155
1305
2135
1305
1775
1.2
1875
85°C
Typ
60
2280
1530
Max
75
2405
1700
2420
1700
1975
3.3
Unit
mA
mV
mV
mV
mV
mV
V
I
IH
I
IL
150
0.5
−150
150
0.5
−150
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to −0.5 V.
7. All loading with 50
W
to V
CC
− 2.0 V.
8. Single−ended input operation is limited to V
CC
3.0 V in PECL mode.
9. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 7. 100LVEP DC CHARACTERISTICS, NECL
V
CC
= 0 V, V
EE
= −3.8 V to −2.375 V (Note 10)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Reference Voltage (Note 12)
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
Input HIGH Current
Input LOW Current
CLK
CLK
0.5
−150
Min
45
−1145
−1995
−1165
−1995
−1525
−1425
Typ
60
−1020
−1770
Max
75
−895
−1600
−880
−1600
−1325
0.0
Min
45
−1145
−1995
−1165
−1995
−1525
−1425
25°C
Typ
60
−1020
−1770
Max
75
−895
−1600
−880
−1600
−1325
0.0
Min
45
−1145
−1995
−1165
−1995
−1525
−1425
85°C
Typ
60
−1020
−1770
Max
75
−895
−1600
−880
−1600
−1325
0.0
Unit
mA
mV
mV
mV
mV
mV
V
V
EE
+ 1.2
V
EE
+ 1.2
V
EE
+ 1.2
I
IH
I
IL
150
0.5
−150
150
0.5
−150
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Input and output parameters vary 1:1 with V
CC
.
11. All loading with 50
W
to V
CC
− 2.0 V.
12. Single−ended input operation is limited to V
EE
3.0 V in NECL mode.
13. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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MC100LVEP14
Table 8. DC CHARACTERISTICS, HSTL
V
CC
= 2.375 V to 3.8 V, V
EE
= 0 V
−40°C
Symbol
V
IH
V
IL
Characteristic
Input HIGH Voltage
Input LOW Voltage
Min
1200
400
Typ
Max
Min
1200
400
25°C
Typ
Max
Min
1200
400
85°C
Typ
Max
Unit
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 9. AC CHARACTERISTICS
V
CC
= 0 V, V
EE
= −2.375 V to −3.8 V or V
CC
= 2.375 V to 3.8 V; V
EE
= 0 V (Note 14)
−40°C
Symbol
V
OUTPP
t
PLH
t
PHL
t
skew
t
s
t
h
t
JITTER
Characteristic
Output Voltage Amplitude @ 2.5 GHz
(Figure 2)
Propagation Delay to
Output Differential
Within−Device Skew (Note 15)
Device−to−Device Skew (Note 15)
Setup Time
Hold Time
CLOCK Random Jitter (RMS)
@
v
1.0 GHz
@
v
1.5 GHz
@
v
2.0 GHz
@
v
2.5 GHz
Minimum Input Swing
Output Rise/Fall Time (20%−80%)
150
125
EN
EN
100
200
Min
330
300
Typ
425
375
10
100
50
140
0.157
0.163
0.180
0.179
800
165
0.3
0.2
0.3
0.3
1200
225
150
125
425
25
125
100
200
Max
Min
280
300
25°C
Typ
375
400
15
150
50
140
0.181
0.176
0.201
0.208
800
180
0.3
0.3
0.3
0.3
1200
250
150
125
475
25
175
100
200
Max
Min
230
300
85°C
Typ
295
430
15
200
50
140
0.212
0.218
0.235
0.253
800
200
0.3
0.3
0.3
0.4
1200
275
mV
ps
525
25
225
Max
Unit
mV
ps
ps
ps
ps
V
PP
t
r
/t
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50
W
to V
CC
− 2.0 V.
15. Skew is measured between outputs under identical transitions.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
− ECL Clock Distribution Techniques
− Designing with PECL (ECL at +5.0 V)
− ECLinPSt I/O SPiCE Modeling Kit
− Metastability and the ECLinPS Family
− Interfacing Between LVDS and ECL
− The ECL Translator Guide
− Odd Number Counters Design
− Marking and Date Codes
− Termination of ECL Logic Devices
− Interfacing with ECLinPS
− AC Characteristics of ECL Devices
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