Revision 16
IGLOO PLUS Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
•
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low Power Active FPGA Operation
Flash*Freeze
Technology
Enables
Ultra-Low
Power
Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW State
per I/O in Flash*Freeze Mode
• Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode
Advanced I/O
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—4 Banks per Chip on All
IGLOO
®
PLUS Devices
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Selectable Schmitt Trigger Inputs
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Small-Footprint Packages across the IGLOO
PLUS Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Feature Rich
• 30 k to 125 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
Reprogrammable Flash Technology
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
Clock Conditioning Circuit (CCC) and PLL
†
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
†
• FlashLock
®
Designed to Secure FPGA Contents
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
†
• True Dual-Port SRAM (except ×18)
†
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Table 1 • IGLOO PLUS Product Family
IGLOO PLUS Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
Secure (AES) ISP
FlashROM Kbits
Integrated PLL in CCCs
1
VersaNet Globals
2
I/O Banks
Maximum User I/Os
Package Pins
CS
VQ
AGLP030
30,000
256
792
5
–
–
–
1
–
6
4
120
CS201, CS289
VQ128
AGLP060
60,000
512
1,584
10
18
4
Yes
1
1
18
4
157
CS201, CS289
VQ176
AGLP125
125,000
1,024
3,120
16
36
8
Yes
1
1
18
4
212
CS281, CS289
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
† The AGLP030 device does not support this feature.
December 2012
© 2012 Microsemi Corporation
I
IGLOO PLUS Low Power Flash FPGAs
I/Os Per Package
1
IGLOO PLUS Devices
Package
CS201
CS281
CS289
VQ128
VQ176
120
–
120
101
–
AGLP030
AGLP060
Single-Ended I/Os
157
–
157
–
137
–
212
212
–
–
AGLP125
Note:
When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
Table 2 • IGLOO PLUS FPGAs Package Size Dimensions
Package
Length × Width (mm/mm)
Nominal Area (mm2)
Pitch (mm)
Height (mm)
CS201
8×8
64
0.5
0.89
CS281
10 × 10
100
0.5
1.05
CS289
14 × 14
196
0.8
1.20
VQ128
14 × 14
196
0.4
1.0
VQ176
20 × 20
400
0.4
1.0
IGLOO PLUS Device Status
IGLOO PLUS Device
AGLP030
AGLP060
AGLP125
Status
Production
Production
Production
II
R evis i o n 16
IGLOO PLUS Low Power Flash FPGAs
IGLOO PLUS Ordering Information
AGLP125
V2
_
CS
G
289
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C ambient temperature)
I = Industrial (
–
40°C to +85°C ambient temperature)
PP = Pre-Production
ES = Engineering Sample (room temperature only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging
Package Type
CS = Chip Scale Package (0.5 mm and 0.8 mm pitches)
VQ = Very Thin Quad Flat Pack (0.4 mm pitch)
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
AGLP030 = 30,000 System Gates
AGLP060 = 60,000 System Gates
AGLP125 = 125,000 System Gates
Notes:
1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked accordingly.
2. "G" indicates RoHS-compliant packages.
R ev i si o n 1 6
III
IGLOO PLUS Low Power Flash FPGAs
Temperature Grade Offerings
Package
CS201
CS281
CS289
VQ128
VQ176
AGLP030
C, I
–
C, I
C, I
–
AGLP060
C, I
–
C, I
–
C, I
AGLP125
–
C, I
C, I
–
–
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/company/contact/default.aspx.
IV
Revision 16
IGLOO PLUS Low Power Flash FPGAs
Table of Contents
IGLOO PLUS Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IGLOO PLUS DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Pin Descriptions and Packaging
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-4
3-5
3-5
3-5
Package Pin Assignments
VQ128
VQ176
CS201
CS281
CS289
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
R ev i si o n 1 6
V
京公网安备 11010802033920号
EEWORLD
