EVALUATION KIT AVAILABLE
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
General Description
The MAX5823/MAX5824/MAX5825 8-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal 3ppm/°C
reference that is selectable to be 2.048V, 2.500V, or
4.096V. The MAX5823/MAX5824/MAX5825 accept a
wide supply voltage range of 2.7V to 5.5V with extremely
low power (6mW) consumption to accommodate most
low-voltage applications. A precision external reference
input allows rail-to-rail operation and presents a 100kI
(typ) load to an external reference.
The MAX5823/MAX5824/MAX5825 have an I
2
C-compatible,
2-wire interface that operates at clock rates up to
400kHz. The DAC output is buffered and has a low sup-
ply current of less than 250FA per channel and a low
offset error of
Q0.5mV
(typ). On power-up, the MAX5823/
MAX5824/MAX5825 reset the DAC outputs to zero or mid-
scale based on the status of M/Z logic input, providing
flexibility for a variety of control applications. The internal
reference is initially powered down to allow use of an
external reference. The MAX5823/MAX5824/MAX5825
allow simultaneous output updates using software LOAD
commands or the hardware load DAC logic input (LDAC).
The MAX5823/MAX5824/MAX5825 feature a watchdog
function which can be enabled to monitor the I/O inter-
face for activity and integrity.
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
simultaneously sets the DAC outputs to the program-
mable default value. The MAX5823/MAX5824/MAX5825
are available in a 20-pin TSSOP and an ultra-small,
20-bump WLP package and are specified over the -40NC
to +125NC temperature range.
Benefits and Features
S
Eight High-Accuracy DAC Channels
12-Bit Accuracy Without Adjustment
LSB INL Buffered Voltage Output
±1
Guaranteed Monotonic Over All Operating
Conditions
Independent Mode Settings for Each DAC
S
Three Precision Selectable Internal References
2.048V, 2.500V, or 4.096V
S
Internal Output Buffer
Rail-to-Rail Operation with External Reference
4.5µs Settling Time
Outputs Directly Drive 2kI Loads
S
Small 6.5mm x 4.4mm 20-Pin TSSOP or Ultra-
Small 2.5mm x 2.3mm 20-Bump WLP Package
S
Wide 2.7V to 5.5V Supply Range
S
Separate 1.8V to 5.5V V
DDIO
Power-Supply Input
S
Fast 400kHz I
2
C-Compatible, 2-Wire Serial
Interface
S
Pin-Selectable Power-On-Reset to Zero-Scale or
Midscale DAC Output
S
LDAC
and
CLR
For Asynchronous DAC Control
S
Three Software-Selectable Power-Down Output
Impedances
1kI, 100kI, or High Impedance
Functional Diagram
V
DDIO
V
DD
REF
INTERNAL REFERENCE/
EXTERNAL BUFFER
SCL
SDA
ADDR0
ADDR1
CLR
LDAC
CODE
IRQ
WATCHDOG
TIMER
CLEAR /
RESET
(GATE/
CLEAR /
RESET)
I
2
C SERIAL
INTERFACE
CODE
REGISTER
DAC
LATCH
8 -/10-/12-BIT
DAC
MAX5823
MAX5824
MAX5825
1 OF 8 DAC CHANNELS
Applications
Programmable Voltage and Current Sources
Gain and Offset Adjustment
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
BUFFER
OUT0
OUT1
OUT2
OUT3
OUT4
LOAD
100kI
DAC CONTROL LOGIC
POWER-DOWN
1kI
OUT5
OUT6
OUT7
M/Z
POR
GND
Ordering Information
appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to:
www.maximintegrated.com/MAX5823.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6185; Rev 2; 2/13
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
ABSOLUTE MAXIMUM RATINGS
V
DD
, V
DDIO
to GND ................................................-0.3V to +6V
OUT_, REF to GND....0.3V to the lower of (V
DD
+ 0.3V) and +6V
SCL, SDA,
IRQ,
M/Z,
LDAC, CLR
to GND .............-0.3V to +6V
ADDR_ to GND............................................-0.3V to the lower of
(V
DDIO
+ 0.3V) and +6V
Continuous Power Dissipation (T
A
= +70NC)
TSSOP (derate at 13.6mW/NC above 70NC) ..............1084mW
WLP (derate at 21.3mW/NC above 70NC) ..................1700mW
Maximum Continuous Current into Any Pin ....................
Q50mA
Operating Temperature .................................... -40NC to +125NC
Storage Temperature ....................................... -65NC to +150NC
Lead Temperature (TSSOP only)(soldering, 10s) ...........+300NC
Soldering Temperature (reflow) .................................... +260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACkAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (θ
JA
) ......73.8NC/W
Junction-to-Case Thermal Resistance (θ
JC
) ..............20NC/W
WLP
Junction-to-Ambient Thermal Resistance (θ
JA
)
(Note 2) ...................................................................47NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Note 2:
Visit
www.maximintegrated.com/app-notes/index.mvp/id/1891
for information about the thermal performance of WLP pack-
aging.
ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI, T
A
= -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
DC PERFORMANCE (Note 4)
MAX5823
Resolution and Monotonicity
N
MAX5824
MAX5825
MAX5823
Integral Nonlinearity (Note 5)
INL
MAX5824
MAX5825
MAX5823
Differential Nonlinearity (Note 5)
Offset Error (Note 6)
Offset Error Drift
Gain Error (Note 6)
Gain Temperature Coefficient
Zero-Scale Error
Full-Scale Error
With respect to V
REF
GE
With respect to V
REF
0
-0.5
-1.0
DNL
OE
MAX5824
MAX5825
8
10
12
-0.25
-0.5
-1
-0.25
-0.5
-1
-5
Q0.05
Q0.2
Q0.5
Q0.05
Q0.1
Q0.2
Q0.5
Q10
Q0.1
Q3.0
+10
+0.5
+1.0
+0.25
+0.5
+1
+0.25
+0.5
+1
+5
mV
FV/NC
%FS
ppm of
FS/NC
mV
%FS
LSB
LSB
Bits
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maxim Integrated
2
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI, T
A
= -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC OUTPUT CHARACTERISTICS
No load
Output Voltage Range (Note 7)
2kI load to GND
2kI load to V
DD
V
DD
= 3V
Q10%,
|I
OUT
|
P
5mA
V
DD
= 5V
Q10%,
|I
OUT
|
P
10mA
V
DD
= 3V
Q10%,
|I
OUT
|
P
5mA
V
DD
= 5V
Q10%,
|I
OUT
|
P
10mA
0
0
0.2
300
FV/mA
300
0.3
I
0.3
500
2
Sourcing (output
shorted to GND)
Sinking (output shorted
to V
DD
)
30
mA
50
100
1.0
2.2
2.6
4.5
7
3.3
4.07
0.2
200
50
nV*s
nV*s
nV*s
Fs
Fs
Fs
FV/V
V/Fs
pF
kI
V
DD
V
DD
-
0.2
V
DD
V
Load Regulation
V
OUT
= V
FS
/2
DC Output Impedance
V
OUT
= V
FS
/2
Maximum Capacitive Load
Handling
Resistive Load Handling
C
L
R
L
V
DD
= 5.5V
Short-Circuit Output Current
DC Power-Supply Rejection
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
DAC Glitch Impulse
Channel-to-Channel Feedthrough
(Note 8)
Digital Feedthrough
Power-Up Time
SR
V
DD
= 3V
Q10%
or 5V
Q10%
Positive and negative
¼ scale to ¾ scale, to
P
1 LSB, MAX5823
¼ scale to ¾ scale, to
P
1 LSB, MAX5824
¼ scale to ¾ scale, to
P
1 LSB, MAX5825
Major code transition (code x7FF to x800)
Internal reference
External reference
Midscale code, all digital inputs from 0V to
V
DDIO
Startup calibration time (Note 9)
From power-down
Maxim Integrated
3
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI, T
A
= -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
f = 1kHz
External reference
f = 10kHz
f = 1kHz
2.048V internal
reference
f = 10kHz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to
External reference
f = 0.1Hz to
f = 0.1Hz to
f = 0.1Hz to
2.048V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 0.1Hz to
2.5V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 0.1Hz to
4.096V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 1kHz
External reference
f = 10kHz
f = 1kHz
2.048V internal
reference
f = 10kHz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to
External reference
f = 0.1Hz to
f = 0.1Hz to
f = 0.1Hz to
2.048V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 0.1Hz to
2.5V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 0.1Hz to
4.096V internal
f = 0.1Hz to
reference
f = 0.1Hz to
MIN
TYP
90
82
112
102
125
110
160
145
12
76
385
14
91
450
15
99
470
16
124
490
114
99
175
153
200
174
295
255
13
94
540
19
143
685
21
159
705
26
213
750
MAX
UNITS
Output Voltage-Noise Density
(DAC Output at Midscale)
nV/√Hz
Integrated Output Noise
(DAC Output at Midscale)
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
FV
P-P
Output Voltage-Noise Density
(DAC Output at Full Scale)
nV/√Hz
Integrated Output Noise
(DAC Output at Full Scale)
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
FV
P-P
Maxim Integrated
4
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI, T
A
= -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
REFERENCE INPUT
Reference Input Range
Reference Input Current
Reference Input Impedance
REFERENCE OUTPUT
Reference Output Voltage
Reference Temperature
Coefficient (Note 10)
Reference Drive Capacity
Reference Capacitive Load
Handling
Reference Load Regulation
Reference Line Regulation
POWER REQUIREMENTS
Supply Voltage
I/O Supply Voltage
V
DD
V
DDIO
V
REF
= 2.048V
Internal reference
Supply Current (Note 11)
I
DD
External reference
V
REF
= 2.5V
V
REF
= 4.096V
V
REF
= 3V
V
REF
= 5V
V
REF
= 4.096V
All other options
4.5
2.7
1.8
1.6
1.7
2.0
1.6
1.9
140
0.7
2
2
4
1
0.7 x
V
DDIO
0.8 x
V
DDIO
0.7 x
V
DD
FA
FA
5.5
5.5
5.5
2
2.1
2.5
2.0
2.5
mA
V
V
I
SOURCE
= 0 to 500FA
V
REF
V
REF
= 2.048V, T
A
= +25NC
V
REF
= 2.5V, T
A
= +25NC
V
REF
= 4.096V, T
A
= +25NC
MAX5825A
MAX5823/MAX5824/MAX5825B
External load
2.043
2.494
4.086
2.048
2.500
4.096
Q3
Q10
25
200
2
0.05
2.053
2.506
4.106
Q10
Q25
ppm/NC
kI
pF
mV/mA
mV/V
V
V
REF
I
REF
R
REF
V
REF
= V
DD
= 5.5V
75
1.24
55
100
V
DD
74
V
FA
kI
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
All DACs off, internal reference ON
Power-Down Mode Supply
Current
I
PD
All DACs off, internal reference OFF,
T
A
= -40NC to +85NC
All DACs off, internal reference OFF,
T
A
= +125NC
I
DDIO
Static logic inputs, all outputs unloaded
Digital Supply Current
DIGITAL INPUT CHARACTERISTICS (SCL, SDA, ADDR0, ADDR1,
LDAC, CLR,
M/Z)
(All inputs except
M/Z)
2.2V < V
DDIO
< 5.5V
1.8V < V
DDIO
< 2.2V
V
Input High Voltage (Note 11)
V
IH
V
2.7V < V
DD
< 5.5V (for M/Z)
Maxim Integrated
5
京公网安备 11010802033920号
EEWORLD
