Edge693
500 MHz Monolithic
Dual Pin Electronics Driver
EDGE HIGH-PERFORMANCE PRODUCTS
Description
The Edge693 is a dual pin electronics driver solution
manufactured in a high-performance, complementary
bipolar process. In Automatic Test Equipment (ATE)
applications, the Edge693 offers two pin drivers suitable
for drive-only channels in memory testers, as well as for
bidirectional channels in memory, VLSI, and mixed- signal
test systems.
Each driver is completely isolated from the other. There
are separate data, enable, slew rate adjust, high and
low levels; as well as power supply inputs for each driver.
The driver output slew rate is adjustable from 3 V/ns to
1 V/ns, allowing the matching of edges from channel-to-
channel, as well as slowing down edges for noise
sensitive applications.
Each driver is capable of driving 9 V signals over a 12 V
range, in addition to going into a high impedance state.
The Edge693 can generate ECL signals up to 500 MHz
and 3V signals in excess of 300 MHz.
Combining two independent drivers into a 28-pin PLCC
package offers a highly integrated solution appropriate
where speed and density are at a premium.
Applications
•
•
Memory Test Equipment
Instrumentation
Functional Block Diagram
SLEWADJA
VCCA GNDA VEEA
DRVENA
DRVENA*
DRIVER A
DHIA
EN
DOUTA
Features
•
•
•
•
•
•
>2.5 V/ns Driver Slew Rates
Adjustable Driver Slew Rates
HiZ Capability
12 V Output Range
9 V Output Swings
28-Pin PLCC with an Internal
Heat Spreader
DHIA*
DVHA
DVLA
BIAS
DRVENB
DRVENB*
DRIVER B
DHIB
EN
DHIB*
DVHB
DVLB
DOUTB
SLEWADJB
VCCB GNDB VEEB
Revision 1 / August 4, 2000
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description
Pin Name
Driver
DRVENA, DRVENA*
DRVENB, DRVENB*
DHIA, DHIA*
DHIB, DHIB*
DOUTA
DOUTB
DVLA, DVHA
DVLB, DVHB
DVLCAPA, DVHCAPA
DVLCAPB, DVHCAPB
SLEWADJA
SLEWADJB
BIAS
Power
VEEA, VEEB
VCCA, VCCB
GNDA, GNDB
Test Pins
THERMAL DIODE
Pin #
Description
25, 24
5, 6
27, 28
3, 2
18
12
22, 23
8, 7
16, 21
14, 9
20
10
1
Wide voltage differential input pins that determine whether the driver (A and B
respectively) is forcing a voltage or placed in a high impedance state.
Wide voltage differential input pins that force one of two programmable levels
(DVH or DVL) at the driver (A and B respectively) output.
Driver A and driver B outputs.
Buffereed analog inputs that program the low and high output levels for driver A
and driver B.
Analog pins. 0.01 µF capacitor to ground should be connected to each pin.
Analog current inputs that adjust the rise and fall slew rates of driver A and
driver B.
Analog input. A positive current into this node sets the internal bias level for
driver A and driver B.
17, 13
19, 11
26, 4
Negative power supply for driver A and driver B.
Positive power supply for driver A and driver B.
Device ground for driver A and driver B.
15
Thermal monitor output used to track the die junction temperature.
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description
(continued)
28-Pin PLCC
SLEWADJA
20
DVHCAPA
DRVENA*
DRVENA
25
24
23
22
21
GNDA
DHIA
DHIA*
BIAS
DHIB*
DHIB
GNDB
26
27
28
1
2
3
4
10
11
5
6
7
8
9
19
VCCA
DVHA
DVLA
18
17
16
15
14
13
12
DOUTA
VEEA
DVLCAPA
THERMAL DIODE
DVLCAPB
VEEB
DOUTB
DRVENB
DVHCAPB
DRVENB*
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SLEWADJB
VCCB
DVHB
DVLB
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description
Introduction
The driver circuit will force the DOUT output to one of
three states:
1.
2.
3.
DVH (driver high voltage level)
DVL (driver low voltage level)
High Impedance (Hi Z).
Driver Levels
DVH and DVL are high-input impedance voltage controlled
inputs that establish the driver logical high and low levels
respectively.
Slew Rate Adjustment
The driver rising and falling slew rates are adjustable
from 3.0 V/ns to 1 V/ns. The SLEWADJ signals are
current controlled inputs that vary the rising and falling
edge slew rates. An input current of 2.0 mA translates
to a slew rate of 3.0 V/ns. An input current of 0.8 mA
forces a 1 V/ns edge (see Figure 1).
Both driver digital control inputs (DHI/DHI*, DRVEN/
DRVEN*) are wide-voltage differential inputs capable of
receiving ECL, TTL, and CMOS signals. Single-ended
operation is achievable by generating the proper
threshold levels for the inverting inputs.
Drive Enable
The drive enable (DRVEN/DRVEN*) inputs control
whether the driver is forcing a voltage or is placed in a
high-impedance state. If DRVEN is more positive than
DRVEN*, the output will force either DVL or DVH,
depending on the driver data inputs. When DRVEN is
more negative than DRVEN*, the output is set to high-
impedance, independent of the driver data inputs.
Driver Data
The driver data inputs (DHI/DHI*) determine whether
the driver output is high or low. If DHI is more positive
than DHI*, the output will force DVH when the driver is
enabled. If DHI is more negative than DHI*, the output
will force DVL when the driver is enabled.
Table 1 summarizes the functionality of the driver enable
and driver data pins.
DRVEN, DRVEN*
DRVEN > DRVEN*
DRVEN > DRVEN*
DRVEN < DRVEN*
DHI, DHI*
DHI > DHI*
DHI < DHI*
X
DOUT
DVH
DVL
HiZ
Slew Rate (V/ns)
2.5
1.0
0.8
2.0
SLEWADJ (mA)
(BIAS = 1.5 mA)
Figure 1. Slew Rate Control
Notice that the driver A slew rate and driver B slew rate
are independent. However, the rising and falling edge
slew rates on each driver track each other and are not
independent (see Figure 2).
a
b
a. SLEWADJ = 2.0 mA, Rising SR = Falling SR = 2.5V/ns.
b. SLEWADJ = 0.8 mA, Rising SR = Falling SR = 1.0V/ns.
Table 1. DRVEN and DHI Pin Functionality
Figure 2. Output Slew Rate Adjustability
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description
(continued)
For system level flexibility, the SLEWADJ input is designed
to allow a voltage DAC, a current DAC, or a resistor to a
fixed voltage as possible slew rate control mechanisms
(see Figure 3).
SLEWADJ
DVLCAP / DVHCAP
These two analog nodes are brought out to better
stabilize the high and low driver levels. Much like placing
decoupling capacitors on the DVL and DVH input pins,
the DVLCAP and DVHCAP pins require a fixed .01
µF
chip capacitor (with good high frequency characteristics)
to ground (see Figure 5). A tight layout with minimum
etch is recommended.
Edge693
1.5KΩ
Rise/Fall
Adjust Current
DVLCAP
.01
µF
DVHCAP
.01
µF
Figure 3. SLEWADJ Inputs
Figure 5. DVLCAP and DVHCAP
Driver Bias
Thermal Monitor
The BIAS pin is an analog current input that requires a
1.2 mA fixed reference current for the driver. Several
circuit configurations are usable to satisfy this
requirement, the most simple being a fixed resistor to a
fixed power supply, typically VCC (see Figure 4). Looking
into the BIAS node shows a .7 V voltage source with a
1.5 KW impedance, so the equation to select the fixed
resistor is:
(VCC – .7) / (R + 1.5) = 1.2 mA
The Edge693 includes an on-chip thermal monitor
accessible through the THERMAL DIODE pin. This node
connects to 5 diodes in series to VEE (see Figure 6) and
may be used to accurately measure the junction
temperature at any time.
Thermal Diode
Bias Current
Alternatively, a current DAC could be used to either
program the BIAS current or to perform subtle
adjustments in the fixed value.
VCC
Edge693
VEE
Temperature coefficient = –10 mV/ C
˚
Figure 6. Thermal Diode String
1.2 mA
R
Bias
A bias current of 100
µA
is injected into this node, and
the measured voltage corresponds to a specific junction
temperature with the following equation:
T
J(˚C)
= {(V
THERMAL DIODE
– VEE) / 5 – .7} / (–.00208).
Figure 4. Bias Current Generation
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