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37LV65TI/L

Description
2K X 32 OTPROM, PQCC20, PLASTIC, LCC-20
Categorystorage    storage   
File Size143KB,14 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

37LV65TI/L Overview

2K X 32 OTPROM, PQCC20, PLASTIC, LCC-20

37LV65TI/L Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQLCC
package instructionPLASTIC, LCC-20
Contacts20
Reach Compliance Codeunknown
Maximum clock frequency (fCLK)10 MHz
I/O typeCOMMON
JESD-30 codeS-PQCC-J20
JESD-609 codee0
memory density65536 bit
Memory IC TypeOTP ROM
memory width32
Number of functions1
Number of terminals20
word count2048 words
character code2000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize2KX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC20,.4SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialSERIAL
power supply3.3/5 V
Certification statusNot Qualified
Maximum standby current0.00005 A
Maximum slew rate0.01 mA
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Base Number Matches1
Obsolete Device
37LV36/65/128
36K, 64K, and 128K Serial EPROM Family
FEATURES
Operationally equivalent to Xilinx
XC1700 family
Wide voltage range 3.0 V to 6.0 V
Maximum read current 10 mA at 5.0 V
Standby current 100
µA
typical
Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
Full Static Operation
Sequential Read/Program
Cascadable Output Enable
10 MHz Maximum Clock Rate @ 5.0 Vdc
Programmable Polarity on Hardware Reset
Programming with industry standard EPROM pro-
grammers
Electrostatic discharge protection > 4,000 volts
8-pin PDIP/SOIC and 20-pin PLCC packages
Data Retention > 200 years
Temperature ranges:
- Commercial: 0°C to +70°C
- Industrial:
-40°C to +85°C
PACKAGE TYPES
PDIP
DATA
CLK
RESET/OE
CE
1
8
V
CC
V
PP
CEO
V
SS
37LV36
37LV65
37LV128
2
3
4
7
6
5
SOIC
DATA
CLK
RESET/OE
CE
1
8
V
CC
V
PP
CEO
V
SS
37LV36
37LV65
37LV128
2
3
4
7
6
5
PLCC
DATA V
CC
20
12
19
18
17
V
PP
16
15
14
CEO
13
3
2
10
1
11
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V V
CC
range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
Device
37LV36
37LV65
37LV128
Bits
36,288
65,536
131,072
Programming Word
1134 x 32
2048 x 32
4096 x 32
CLK
4
5
37LV36
37LV65
37LV128
9
RESET/OE
6
7
CE
8
Vss
BLOCK DIAGRAM
Xilinx is a registered trademark of Xilinx Corporation.
2004 Microchip Technology Inc.
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