MT90401
SONET/SDH System Synchronizer
Data Sheet
Features
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Meets requirements of GR-253-CORE for SONET
Stratum 3 and SONET minimum clock
Meets requirements of GR-1244-CORE Stratum 3
Meets requirements of G.813 Option 1 and Option
2 for SDH Equipment Clocks (SEC) with external
jitter attenuator
Provides OC-3/STM-1, DS3, E3, 19.44 MHz,
DS2, E1, T1, 8 kHz and ST-BUS clock outputs
Accepts reference inputs from two independent
sources
Selectable 1.544 MHz, 2.048 MHz, 19.44 MHz or
8kHz input reference frequencies
Holdover accuracy of 0.02 ppm
Adjustable output clock phase supporting master-
slave arrangements
Hardware or microprocessor control (8 bit
microprocessor interface)
3.3 V supply
JTAG boundary scan
Ordering Information
MT90401AB
80 Pin LQFP
MT90401AB1 80 Pin LQFP*
*Pb Free Matte Tin
-40°C to +85°C
Trays
Trays
January 2005
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Applications
•
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SONET/SDH Add/Drop multiplexers
SONET/SDH uplinks
Integrated access devices
ATM edge switches
Description
The MT90401 is a digital phase locked loop (DPLL)
that is designed to synchronize SDH (Synchronous
Digital Hierarchy) and SONET (Synchronous Optical
Network) networking equipment. The MT90401 is used
to ensure that the timing of outgoing signals remains
within the limits specified by Telcordia, ANSI and the
ITU during normal operation and in the presence of
disturbances on the incoming synchronization signals.
LOCK
VDD
VSS
TCLR
C20i
TCK
TDI
TMS
TRST
TDO
PRI
SEC
Prioor
Secoor
Master Clock
IEEE
1149.1a
TIE
Corrector
Circuit
Selected
Refer-
ence
TIE
Corrector
Enable
Reference
Select
Virtual
Reference
DPLL
Output
Interface
Circuit
State
Select
Input
Impairment
Monitor
Reference
Select
MUX
Reference
Monitor
State
Select
C155P/N
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
C44/C34
F0o
F8o
F16o
Feedback
Frequency
Select
MUX
RSEL
Control State Machine
RST MS1 MS2 HOLDOVER PCCi FLOCK D0/D7 A0/A6 CS,DS,R/W
FS1
FS2
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT90401
Data Sheet
The MT90401 can operate in free-run, locked or holdover mode. The loop filter corner frequency can be selected to
suit SONET applications or to suit SDH applications. The MT90401 uses an external 20 MHz oscillator as its
master clock and it does not require external loop filter components.
In Hardware Mode, the MT90401 can be controlled and monitored via external pins. In Microport Mode, a
microprocessor can be used for more comprehensive control and monitoring.
IC
DS
FLOCK
LOCK
PCCi
HOLDOVER
VDD4
C34/C44
VSS7
C20i
NC
VDD3
TCLR
RSEL
C19o
VSS5
IC
C6o
C1.5o
PRIOOR
60
62
64
36
66
34
68
32
70
72
28
74
26
76
24
78
22
80
2
4
6
8
10
12
14
16
18
20
58
56
54
52
50
48
46
44
42 40
38
SECOOR
OE
CS
RST
HW
D0
D1
D2
D3
VSS8
IC
IC
VDD5
D4
D5
D6
D7
R/W
A0
IC
MT90401AB
30
FS1
FS2
Tdi
Trst
Tclk
Tms
Tdo
VREF
VSS4
C155P
C155N
VDD
VDD2
VSS3
IC
VSS2
PRI
SEC
E3/DS3
E3DS3/OC3
IC
A1
A2
A3
A4
VSS9
A5
A6
SONET/SDH
VDD1
VSS1
F16o
C16o
C8o
C4o
C2o
F0o
Figure 2 - Pin Connections 80 Pin LQFP for MT90401
2
Zarlink Semiconductor Inc.
MS1
MS2
F8o
MT90401
Pin Description
Pin #
1
2-5
6
7, 8
9
Name
IC
A1 - A4
V
SS9
A5, A6
Description
Internal Connection.
Leave unconnected.
Data Sheet
Address 1 to 4 (5 V tolerant Inputs).
Address inputs for the parallel processor interface.
Digital ground.
0 Volts
Address 5, to 6 (5 V tolerant Input).
Address inputs for the parallel processor interface.
SONET/SD
SONET/SDH (Input).
In hardware mode set this pin high to have a loop filter corner
H
frequency of 70 millihertz and limit the phase slope to 885 ns per second. Set this pin low to
have a corner frequency of approximately 1.1 hertz and limit the phase slope to 53 ns per
1.326 ms. This pin performs no function if the device is not in hardware mode.
V
DD1
V
SS1
F16o
Positive Power Supply.
Digital supply.
Digital ground.
0 Volts
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8kHz 61ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 8.192 Mb/s.
Clock 16.384 MHz (CMOS Output).
This output is used for ST-BUS operation with a
16.384 MHz clock.
Clock 8.192 MHz (CMOS Output).
This output is used for ST-BUS operation at
8.192 Mb/s.
Clock 4.096 MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
Clock 2.048 MHz (CMOS Output).
This output is used for ST-BUS operation at
2.048 Mb/s.
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output).
This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048 Mb/s and 4.096 Mb/s.
Mode/Control Select 1 (Input).
This input, together with MS2, determines the state
(Normal, Holdover, or Freerun) of operation. See Table 3 on page 15. The logic level at this
input is gated in by the rising edge of F8o. This pin performs no function if the device is not
in hardware mode.
Mode/Control Select 2 (Input).
This input, together with MS1, determines the state
(Normal, Holdover or Freerun) of operation. See Table 3 on page 15. The logic level at this
input is gated in by the rising edge of F8o. This pin performs no function if the device is not
in hardware mode.
Frame Pulse Generic (CMOS Output).
This is an 8 kHz 122 ns active high framing pulse,
which marks the beginning of a TDM frame. This is typically used for TDM streams
operating at 8.192 Mb/s.
10
11
12
13
14
15
16
17
C16o
C8o
C4o
C2o
F0o
18
MS1
19
MS2
20
F8o
21
E3DS3/OC3
E3DS3 or OC-3 Selection (Input).
In Hardware Mode a low on this pin enables the
differential 155.52 MHz output clock on the C155N/C155P pins; this will also cause the
C34/C44 pin to output its nominal clock frequency divided by 4. In Hardware Mode, a high
on this pin disables the differential 155.52 MHz output clock on the C155N/C155P pins; this
will also cause the C34/C44 pin to output its nominal clock frequency. This pin performs no
function if the device is not in Hardware Mode.
3
Zarlink Semiconductor Inc.
MT90401
Pin Description (continued)
Pin #
22
Name
E3/DS3
Description
Data Sheet
E3 or DS3 Selection (Input).
In Hardware Mode a low on this pin selects a clock rate of
44.736 MHz for the C34/C44 pin, while a high selects a clock rate of 34.368 MHz. This pin
performs no function if the device is not in hardware mode.
Secondary Reference (Input).
This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies ( 8kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the
input reference is based upon the MS1, MS2 and RSEL control inputs.
Primary Reference (Input).
This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies (8 kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the
input reference is based upon the MS1, MS2 and RSEL control inputs.
Digital ground.
0 Volts
Internal Connection.
Leave unconnected
Analog ground.
0 Volts
Positive Analog Power Supply.
Analog supply.
Positive Power Supply.
Digital supply.
LVDS 155.52 MHz (Output)).
Differential outputs generating a 155.52 MHz clock
Digital ground.
0 Volts
LVDS Reference Voltage (Input).
IEEE 1149.1a Test Data Output (Output).
If not used, this pin should be left unconnected.
IEEE 1149.1a Test Mode Selection (Input).
If not used, this pin should be pulled high.
IEEE 1149.1a Test Clock Signal (Input).
If not used, this pin should be pulled high.
IEEE 1149.1a Reset Signal (Input).
If not used, this pin should be held low.
IEEE 1149.1a Test Data Input (Input).
If not used, this pin should be pulled high.
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. For more details see FS2 bit description in Table 6 - Control Register 1
(Address 00H - Read/Write).
Frequency Select 1 (Input).
This input, in conjunction with FS2, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. For more details see FS1 bit description in Table 6 - Control Register 1
(Address 00H - Read/Write).
Primary Reference Out Of Range (CMOS Output).
A logic high at this pin indicates that
the primary reference is off the PLL center frequency by more than 12 ppm. The
measurement is done on a 1 second basis using a signal derived from the 20 MHz clock
input on C20i. When the accuracy of the 20 MHz clock is
±
4.6 ppm, the effective out of
range limits of the PRIOOR signal will be
+
16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.
Clock 1.544 MHz (CMOS Output).
This output is used in T1 applications.
Clock 6.312 MHz (CMOS Output).
This output is used for DS2 or J2 applications.
Internal Connection.
Tie low for normal operation.
23
SEC
24
PRI
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
V
SS2
IC
V
SS3
V
DD2
V
DD
C155N,
C155P
V
SS4
VREF
Tdo
Tms
Tclk
Trst
Tdi
FS2
40
FS1
41
PRIOOR
42
43
44
C1.5o
C6
IC
4
Zarlink Semiconductor Inc.
MT90401
Pin Description (continued)
Pin #
45
46
47
Name
V
SS5
C19o
RSEL
Digital ground.
0 Volts
Description
Data Sheet
Clock 19.44 MHz (CMOS Output).
This output is used in OC-N and STM-N applications.
Reference Source Select (Input).
A logic low selects the PRI (primary) reference source
as the input reference signal and a logic high selects the SEC (secondary) input. The logic
level at this input is gated in by the rising edge of F8o. For more details see RSEL bit
description in Table 6 - Control Register 1 (Address 00H - Read/Write).
TIE Circuit Clear (Input).
A logic low at this input clears the Time Interval Error (TIE)
correction circuit resulting in a realignment of output phase with input phase. The TCLR pin
should be held low for a minimum of 300 ns. When this pin is held low, the time interval error
correction circuit is disabled.
Positive Power Supply. Digital supply.
No Connection.
20 MHz Clock Input (5 V tolerant Input).
This pin is the input for the master 20 MHz clock.
Digital ground.
0Volts
Controlled Clock 34.368 MHz / Clock 44.736 MHz (CMOS Output).
This output clock is
programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz (for DS3
applications). The output clock is controlled via control pins in Hardware Mode or control
bits when the device is in Microport Mode.
If the E3DS3/OC3 control pin or control bit is high, the C34/C44 pin will output its nominal
frequency. If the E3DS3/OC3 control pin or bit is low, the C34/C44 pin will output its nominal
frequency divided by 4. (C8.5o/C11o)
48
TCLR
49
50
51
52
53
V
DD3
NC
C20i
V
SS7
C34/C44
54
55
56
V
DD4
PCCi
Positive Power Supply.
Digital supply.
Phase Continuity Control Input (3 V Input).
The signal at this pin affects the state
changes between Primary Holdover Mode and Primary Normal Mode and Primary Holdover
Mode and Secondary Normal Mode. The logic level at this input is gated by the rising edge
of F8o. See Figure 12, “Control State Diagram” on page 21 for details.
Lock Indicator (CMOS Output).
This output goes high when the PLL is in frequency lock
to the input reference.
Fast Lock Mode (Input).
In hardware mode, hold this pin high to lock faster than normal to
the input reference. This pin performs no function if the device is not in hardware mode. In
Fast Lock Mode, the wander generation of the PLL is, of necessity, compromised.
Data Strobe (5 V tolerant Input).
This input is the active low data strobe of the Motorola
processor interface.
Internal Connection.
Tie low for normal operation.
Secondary Reference Out Of Capture Range (CMOS Output).
A logic high at this pin
indicates that the secondary reference is off the PLL center frequency by more than 12
ppm. The measurement is done on a 1 second basis using a signal derived from the
20 MHz clock input on the C20i pin. When the accuracy of the 20 MHz clock is
±
4.6 ppm
the effective out of range limits of the SECOOR signal will be
+
16.6 ppm to -7.4 ppm or
+7.4 ppm to -16.6 ppm.
HOLDOVER
Holdover (CMOS Output).
This output goes high when the device is in holdover mode.
57
58
LOCK
FLOCK
59
60
61
DS
IC
SECOOR
5
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