MT8981D datasheet, PDF - EEWORLD Datasheet

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MT8981D: DescriptionISO-CMOS ST-BUS; File Size472KB，20 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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MT8981D Overview

ISO-CMOS ST-BUS

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ISO-CMOS ST-BUS

Family

MT8981D

Digital Switch

Data Sheet

Features

•

Zarlink ST-BUS compatible

4-line x 32-channel inputs

4-line x 32-channel outputs

128 ports non-blocking switch

Single power supply (+5 V)

Low power consumption: 30 mW Typ.

Microprocessor-control interface

Three-state serial outputs

Ordering Information

MT8981DE

40 Pin PDIP

MT8981DP

44 Pin PLCC

MT8981DPR

44 Pin PLCC

MT8981DP1 44 Pin PLCC*

MT8981DPR1 44 Pin PLCC*

*Pb Free Matte Tin

February 2005

Tubes

Tape & Reel

Tubes

Tape & Reel

-40°C to +85°C

Description

This VLSI ISO-CMOS device is designed for switching

PCM-encoded voice or data, under microprocessor

control, in a modern digital exchange, PBX or Central

Office. It provides simultaneous connections for up to

128 64 kbit/s channels. Each of the four serial inputs

and outputs consist of 32 64 kbit/s channels

multiplexed to form a 2048 kbit/s ST-BUS stream. In

addition, the MT8981 provides microprocessor read

and write access to individual ST-BUS channels.

C4i

F0i

ODE

STi0

STi1

STi2

STi3

Serial

Parallel

Converter

Data

Memory

Frame

Counter

Output

MUX

Parallel

Serial

Converter

STo0

STo1

STo2

STo3

Control Register

Connection

Memory

Control Interface

DS CS

R/W A5/

DTA D7/

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT8981D

Hardware Description

Data Sheet

Serial data at 2048 kbit/s is received at the four ST-BUS inputs (STi0 to STi3), and serial data is transmitted at the

four ST-BUS outputs (STo0 to STo3). Each serial input accepts 32 channels of digital data, each channel containing

an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., Zarlink’s

MT8964).

This serial input word is converted into parallel data and stored in the 128 X 8 Data Memory. Locations in the Data

Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read

by the microprocessor which controls the chip.

Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS

output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either

be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input,

then the contents of the Connection Memory Low location associated with the output channel is used to address

the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the

data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode),

then the contents of the Connection Memory Low location associated with the output channel are output directly,

and this data is output repetitively on the channel once every frame until the microprocessor intervenes.

The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives

address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are

two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the

Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the

address lines directly.

The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel

into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the

Connection Memory Low. The Connection Memory High determines whether individual output channels are in

Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of

MT8981s to be constructed. It also controls the CSTo pin.

All ST-BUS timing is derived from the two signals C4i and F0i.

Zarlink Semiconductor Inc.

MT8981D Related Products

	MT8981D	MT8981DPR1	MT8981DP1	MT8981DPR	MT8981DP	MT8981DE
Description	ISO-CMOS ST-BUS	ISO-CMOS ST-BUS	ISO-CMOS ST-BUS	ISO-CMOS ST-BUS	ISO-CMOS ST-BUS	ISO-CMOS ST-BUS
Is it Rohs certified?	-	conform to	conform to	incompatible	incompatible	incompatible
Maker	-	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)
package instruction	-	QCCJ,	QCCJ,	QCCJ, LDCC44,.7SQ	QCCJ, LDCC44,.7SQ	DIP, DIP40,.6
Reach Compliance Code	-	compli	compli	compli	compli	compli
JESD-30 code	-	S-PQCC-J44	S-PQCC-J44	S-PQCC-J44	S-PQCC-J44	R-PDIP-T40
JESD-609 code	-	e3	e3	e0	e0	e0
length	-	16.585 mm	16.585 mm	16.585 mm	16.585 mm	51.75 mm
Humidity sensitivity level	-	3	3	1	1	-
Number of functions	-	1	1	1	1	1
Number of terminals	-	44	44	44	44	40
Maximum operating temperature	-	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	QCCJ	QCCJ	QCCJ	QCCJ	DIP
Package shape	-	SQUARE	SQUARE	SQUARE	SQUARE	RECTANGULAR
Package form	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	IN-LINE
Peak Reflow Temperature (Celsius)	-	260	260	225	225	225
Certification status	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	4.57 mm	4.57 mm	4.57 mm	4.57 mm	6.35 mm
Nominal supply voltage	-	5 V	5 V	5 V	5 V	5 V
surface mount	-	YES	YES	YES	YES	NO
technology	-	CMOS	CMOS	CMOS	CMOS	CMOS
Telecom integrated circuit types	-	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH
Temperature level	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	-	MATTE TIN	MATTE TIN	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	-	J BEND	J BEND	J BEND	J BEND	THROUGH-HOLE
Terminal pitch	-	1.27 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm
Terminal location	-	QUAD	QUAD	QUAD	QUAD	DUAL
Maximum time at peak reflow temperature	-	30	30	30	30	30
width	-	16.585 mm	16.585 mm	16.585 mm	16.585 mm	15.24 mm

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