MT88E45
4-Wire Calling Number Identification
Circuit 2 (4-Wire CNIC2)
Data Sheet
Features
•
Compatible with:
•
•
•
•
Bellcore GR-30-CORE, SR-TSV-002476,
ANSI/TIA/EIA-716, TIA/EIA-777;
ETSI ETS 300 778-1 (FSK only variant) & -2;
BT (British Telecom) SIN227 & SIN242
Ordering Information
MT88E45BN
MT88E45BS
MT88E45BSR
MT88EBNR
MT88E45BN1
MT88E45BNR1
*Pb
20 Pin SSOP
20 Pin SOIC
20 Pin SOIC
20 Pin SSOP
20 Pin SSOP*
20 Pin SSOP*
Free Matte Tin
Tubes
Tubes
Tape & Reel
Tape & Reel
Tubes
Tape & Reel
August 2005
Bellcore ‘CPE Alerting Signal’ (CAS), ETSI ‘Dual
Tone Alerting Signal’ (DT-AS), BT Idle State and
Loop State ‘Tone Alert Signal’ detection
1200 baud Bell 202 and CCITT V.23 FSK
demodulation
Separate differential input amplifiers with
adjustable gain for Tip/Ring and telephone hybrid
or speech IC connections
Selectable 3-wire FSK data interface (bit stream
or 1 byte buffer)
Facility to monitor the stop bit for framing error
check
FSK Carrier detect status output
3 to 5V +/- 10% supply voltage
Uses 3.579545 MHz crystal or ceramic resonator
Low power CMOS with power down
•
•
-40°C to +85°C
•
•
Applications
•
Bellcore CID (Calling Identity Delivery) and
CIDCW (Calling Identity Delivery on Call Waiting)
telephones and adjuncts
ETSI, BT CLIP (Calling Line Identity Presentation)
and CLIP with Call Waiting telephones and
adjuncts
Fax and answering machines
Computer Telephony Integration (CTI) systems
•
•
•
•
•
•
•
FSKen+Tip/Ring CASen
IN1+
IN1-
GS1
IN2+
IN2-
GS2
V
REF
Bias
Generator
PWDN
Oscillator
+
-
Hybrid CASen
MODE
FSKen
PWDN
CASen
MODE
FSK
Bandpass
FSKen
CASen
2130Hz
Bandpass
2750Hz
Bandpass
Mux
Carrier
Detector
DR
STD
Tone
Detection
Algorithm
Guard
Time
FSK
Demodulator
Data Timing
Recovery
DATA
DCLK
CD
DR/STD
+
-
PWDN
PWDN
Anti-Alias
Filter
PWDN
ST/GT
EST
Vdd
Vss
Control Bit
Decode
CASen
CB0 CB1 CB2
OSC1
OSC2
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT88E45
Description
Data Sheet
The MT88E45B is a low power CMOS integrated circuit suitable for receiving the physical layer signals used in
North American (Bellcore) Calling Identity Delivery on Call Waiting (CIDCW) and Calling Identity Delivery (CID)
services. It is also suitable for ETSI and BT Calling Line Identity Presentation (CLIP) and CLIP with Call Waiting
services.
The MT88E45B contains a 1200 baud Bell 202/CCITT V.23 FSK demodulator and a CAS/DT-AS detector. Two
input op-amps allow the MT88E45B to be connected to both Tip/Ring and the telephone hybrid or speech IC
receive pair for optimal CIDCW telephone architectural implementation. FSK demodulation is always on Tip/Ring,
while CAS detection can be on Tip/Ring or Hybrid Receive. Tip/Ring CAS detection is required for the Bellcore/TIA
Multiple Extension Interworking (MEI) and BT’s on-hook CLIP. A selectable FSK data interface allows the data to be
processed as a bit stream or extracted from a 1 byte on chip buffer. Power management has been incorporated to
power down the FSK or CAS section when not required. Full chip power down is also available. The MT88E45B is
suitable for applications using a fixed power source (with a +/-10% variation) between 3 and 5 V.
2
Zarlink Semiconductor Inc.
MT88E45
Data Sheet
V
REF
IN1+
IN1-
GS1
Vss
OSC1
OSC2
CB0
DCLK
DATA
1
2
3
4
5
6
7
8
9
10
MT88E45B
20
19
18
17
16
15
14
13
12
11
IN2+
IN2-
GS2
CB2
CB1
Vdd
CD
ST/GT
EST
DR/STD
Figure 2 - Pin Connections
Pin Description
Pin # Name
1
2
3
4
V
REF
IN1+
IN1-
GS1
Description
Voltage Reference (Output).
Nominally Vdd/2. It is used to bias the Tip/Ring and Hybrid input op-
amps.
Tip/Ring Op-amp Non-inverting (Input).
Tip/Ring Op-amp Inverting (Input).
Tip/Ring Gain Select (Output).
This is the output of the Tip/Ring connection op-amp. The op-
amp should be used to connect the MT88E45B to Tip and Ring. The Tip/Ring signal can be
amplified or attenuated at GS1 via selection of the feedback resistor between GS1 and IN1-. FSK
demodulation (which is always on Tip/Ring) or CAS detection (for MEI or BT on-hook CLIP) of the
GS1 signal is enabled via the CB1 and CB2 pins. See Tables 1 and 2.
Power supply ground.
5
6
7
8
Vss
OSC1
Oscillator (Input).
Crystal connection. This pin can also be driven directly from an external clock
source.
OSC2
Oscillator (Output).
Crystal connection. When OSC1 is driven by an external clock, this pin
should be left open.
CB0
Control Bit 0 (CMOS Input).
This pin is used primarily to select the 3-wire FSK data interface
mode. When it is low, interface mode 0 is selected where the FSK bit stream is output directly.
When it is high, interface mode 1 is selected where the FSK byte is stored in a 1 byte buffer which
can be read serially by the application’s microcontroller.
The FSK interface is consisted of the DATA, DCLK and DR/STD pins. See the 3 pin descriptions
to understand how CB0 affects the FSK interface.
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state
consuming minimal power supply current. See Tables 1 and 2.
9
DCLK
3-wire FSK Interface Data Clock (Schmitt Input/CMOS Output).
In mode 0 (when the CB0 pin
is logic low) this is a CMOS output which denotes the nominal mid-point of a FSK data bit.
In mode 1 (when the CB0 pin is logic high) this is a Schmitt trigger input used to shift the FSK data
byte out to the DATA pin.
3
Zarlink Semiconductor Inc.
MT88E45
Pin Description
Pin # Name
10
DATA
Description
Data Sheet
3-wire FSK Interface Data (CMOS Output).
Mark frequency corresponds to logical 1. Space
frequency corresponds to logical 0.
In mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to the DATA pin
directly.
In mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte and the trailing
stop bit are stored in a 9 bit buffer. At the end of each word signalled by the DR/STD pin, the
microcontroller should shift the byte out onto the DATA pin by applying 8 read pulses to the DCLK
pin. A 9th DCLK pulse will shift out the stop bit for framing error checking.
11
DR/STD
3-wire FSK Interface Data Ready/CAS Detection Delayed Steering (CMOS Output).
Active
low.
When FSK demodulation is enabled via the CB1 and CB2 pins this pin is the Data Ready output.
It denotes the end of a word. In both FSK interface modes 0 and 1, it is normally hi and goes low
for half a bit time at the end of a word. But in mode 1 if DCLK starts during DR low, the first rising
edge of the DCLK input will return DR to high. This feature allows an interrupt requested by a low
going DR to be cleared upon reading the first DATA bit.
When CAS detection is enabled via the CB1 and CB2 pins this pin is the Delayed Steering output.
It goes low to indicate that a time qualified CAS has been detected.
EST
CAS Detection Early Steering (CMOS Output).
Active high. This pin is the raw CAS detection
output. It goes high to indicate the presence of a signal meeting the CAS accept frequencies and
signal level. It is used in conjunction with the ST/GT pin and external components to time qualify
the detection to determine whether the signal is a real CAS.
12
13
ST/GT
CAS Detection Steering/Guard Time (CMOS Output/Analog Input).
It is used in conjunction
with the EST pin and external components to time qualify the detection to determine whether the
signal is a real CAS.
A voltage greater than V
TGt
at this pin causes the MT88E45B to indicate that a CAS has been
detected by asserting the DR/STD pin low. A voltage less than V
TGt
frees up the MT88E45B to
accept a new CAS and returns DR/STD to high.
CD
Carrier Detect (CMOS Output).
Active low.
A logic low indicates that an FSK signal is present. A time hysteresis is provided to allow for
momentary signal discontinuity. The demodulated FSK data is ignored by the MT88E45B until
carrier detect has been activated.
Positive power supply.
Control Bit 1 (CMOS Input).
Together with CB2 this pin selects the MT88E45B’s functionality
between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state
consuming minimal power supply current. See Tables 1 and 2.
Control Bit 2 (CMOS Input).
Together with CB1 this pin selects the MT88E45B’s functionality
between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state
consuming minimal power supply current. See Tables 1 and 2.
Hybrid Gain Select (Output).
This is the output of the hybrid receive connection op-amp. The op-
amp should be used to connect the MT88E45B to the telephone hybrid or speech IC receive pair.
The hybrid receive signal can be amplified or attenuated at GS2 via selection of the feedback
resistor between GS2 and IN2-. When the CPE is off-hook CAS detection of the GS2 signal
should be enabled via the CB1 and CB2 pins. See Tables 1 and 2.
Hybrid Op-amp Inverting (Input).
Hybrid Op-amp Non-Inverting (Input).
14
15
16
Vdd
CB1
17
CB2
18
GS2
19
20
IN2-
IN2+
4
Zarlink Semiconductor Inc.
MT88E45
FSK
Interface
Data Sheet
CB0 CB1 CB2
0/1
0/1
0/1
1
1
0
1
0
1
Function
Set by CB0 FSK Demodulation. Tip/Ring input (GS1) selected. DR/STD is DR.
Set by CB0 Hybrid CAS Detection. Hybrid Receive input (GS2) selected. DR/STD is STD.
Set by CB0 Tip/Ring CAS Detection. Tip/Ring input (GS1) selected. DR/STD is STD.
When the line is off-hook, a Bellcore/TIA Multiple Extension Interworking (MEI)
compatible Type 2 CPE should be able to detect CAS from Tip/Ring while the
CPE is on-hook because it may be the ACK sender. Tip/Ring CAS detection is
also required for BT’s on-hook CLIP.
Mode 1
Mode 0
Power Down. The MT88E45B is disabled and draws virtually no power supply
current.
Reserved for factory testing.
Table 1 - CB0/1/2 Functionality
1
0
0
0
0
0
The number of control bits (CB) required to interface the MT88E45B with the microcontroller depends on the
functionality of the application, as shown in Table 2.
Functionality Group
FSK (mode 0 or 1) and
Hybrid CAS only
(Non MEI compatible)
Controls
CB2
Description
CB0 is hardwired to Vdd or Vss to select the FSK
interface.
CB1 hardwired to Vdd.
The microcontroller uses CB2 to select between the 2
functions.
CB0 is hardwired to Vdd or Vss to select the FSK
interface.
The microcontroller uses CB1 and CB2 to select between
the 3 functions.
CB0 is hardwired to Vdd to select FSK interface mode 1.
The microcontroller uses CB1 and CB2 to select between
the 4 functions.
FSK (mode 0 or 1),
Hybrid CAS,
Tip/Ring CAS
(MEI compatible or BT on-hook CLIP)
FSK (mode 1),
Hybrid CAS,
Tip/Ring CAS,
Power Down
(MEI compatible or BT on-hook CLIP)
FSK (mode 0), Hybrid CAS,
Tip/Ring CAS, Power Down
(MEI compatible or BT on-hook CLIP)
CB1
CB2
CB1
CB2
CB0
CB1
CB2
All 3 pins are required.
Table 2 - Control Bit Functionality Groups
Functional Overview
The MT88E45B is compatible with FSK and FSK plus CAS (CPE Alerting Signal) based Caller ID services around
the world. Caller ID is the generic name for a group of services offered by telephone operating companies whereby
information about the calling party is delivered to the subscriber. In Europe and some other countries Caller ID is
known as Calling Line Identity Presentation (CLIP). ETSI calls CAS ‘Dual Tone Alerting Signal’ (DT-AS), BT calls it
‘Tone Alert Signal’.
Depending on the service, data delivery can occur when the line is in the on-hook or off-hook state. In most
countries the data is modulated in either Bell 202 or CCITT V.23 FSK format and transmitted at 1200 baud from the
serving end office to the subscriber’s terminal. Additionally in off-hook signalling, the special dual tone CAS is used
5
Zarlink Semiconductor Inc.
京公网安备 11010802033920号
EEWORLD
