4 MEG x 16
EDO DRAM
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x16 pinout, timing, functions,
and package
• 12 row, 10 column addresses (R6)
13 row, 9 column addresses (N3)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
MT4LC4M16R6, MT4LC4M16N3
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Top View)
50-Pin TSOP
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
V
CC
WE#
RAS#
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
V
CC
†
A12
OPTIONS
• Plastic Package
50-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
4K
8K
Standard Refresh
Self Refresh
• Operating Temperature Range
Commercial (0°C to +70°C)
Extended (-40°C to +85°C)
MARKING
TG
-5
-6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
V
SS
CASL#
CASH#
OE#
NC
NC
NC/A12
†
A11
A10
A9
A8
A7
A6
V
SS
R6
N3
None
S*
for N3 version, NC for R6 version.
MT4LC4M16R6
Configuration
Refresh
Row Address
Column Addressing
4 Meg x 16
4K
4K (A0-A11)
1K (A0-A9)
MT4LC4M16N3
4 Meg x 16
8K
8K (A0-A12)
512 (A0-A8)
None
IT**
NOTE:
1. The “#” symbol indicates signal is active LOW.
*Contact factory for availability.
**Available only on MT4LC4M16R6 standard refresh device.
Part Number Example:
4 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC4M16R6TG-x
MT4LC4M16R6TG-x S
MT4LC4M16N3TG-x
MT4LC4M16N3TG-x S
x = speed
REFRESH
ADDRESSING PACKAGE REFRESH
4K
4K
8K
8K
400-TSOP Standard
400-TSOP
Self
400-TSOP Standard
400-TSOP
Self
MT4LC4M16R6TG-5
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
FUNCTIONAL BLOCK DIAGRAM
MT4LC4M16R6 (12 row addresses)
WE#
CASL#
CASH#
CAS#
DATA-IN BUFFER
16
DQ0-
DQ15
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
16
OE#
16
10
COLUMN-
ADDRESS
BUFFER(10)
REFRESH
CONTROLLER
16
10
COLUMN
DECODER
1,024
SENSE AMPLIFIERS
I/O GATING
1,024 x 16
A0-
A11
REFRESH
COUNTER
ROW SELECT
12
12
ROW-
ADDRESS
BUFFERS (12)
ROW
DECODER
COMPLEMENT
SELECT
12
4,096
4,096 x 16
4,096 x 1,024 x 16
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
FUNCTIONAL BLOCK DIAGRAM
MT4LC4M16N3 (13 row addresses)
WE#
CASL#
CASH#
CAS#
DATA-IN BUFFER
16
DQ0-
DQ15
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
16
OE#
16
9
COLUMN-
ADDRESS
BUFFER(9)
REFRESH
CONTROLLER
16
9
COLUMN
DECODER
512
SENSE AMPLIFIERS
I/O GATING
512 x 16
A0-
A12
REFRESH
COUNTER
ROW SELECT
13
13
ROW-
ADDRESS
BUFFERS (13)
COMPLEMENT
SELECT
ROW
DECODER
13
8192
8192 x 16
8192 x 512 x 16
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
Vcc
Vss
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
GENERAL DESCRIPTION
The 4 Meg x 16 DRAM is a high-speed CMOS,
dynamic random-access memory device containing
67,108,864 bits and designed to operate from 3V to
3.6V. The device is functionally organized as 4,194,304
locations containing 16 bits each. The 4,194,304
memory locations are arranged in 4,096 rows by 1,024
columns on the MT4LC4M16R6 or 8,192 rows by 512
columns on the MT4LC4M16N3. During READ or WRITE
cycles, each location is uniquely addressed via the
address bits: 12 row-address bits (A0-A11) and 10
column-address bits (A0-A9) on the MT4LC4M16R6 or
13 row-address bits (A0-A12) and 9 column-address bits
(A0-A8) on the MT4LC4M16N3 version. In addition,
both byte and word accesses are supported via the two
CAS# pins (CASL# and CASH#).
The CAS# functionality and timing related to ad-
dress and control functions (e.g., latching column
addresses or selecting CBR REFRESH) is such that the
internal CAS# signal is determined by the first external
CAS# signal (CASL# or CASH#) to transition LOW and
the last to transition back HIGH. The CAS# functional-
ity and timing related to driving or latching data is such
that each CAS# signal independently controls the asso-
ciated eight DQ pins.
The row address is latched by the RAS# signal, then
the column address is latched by CAS#. This device
provides EDO-PAGE-MODE operation, allowing for fast
successive data operations (READ, WRITE or READ-
MODIFY-WRITE) within a given row.
The 4 Meg x 16 DRAM must be refreshed periodi-
cally in order to retain stored data.
DRAM ACCESS
Each location in the DRAM is uniquely addressable,
as mentioned in the General Description. Use of both
CAS# signals results in a word access via the 16 I/O pins
(DQ0-DQ15). Using only one of the two signals results
in a BYTE access cycle. CASL# transitioning LOW se-
lects an access cycle for the lower byte (DQ0-DQ7), and
CASH# transitioning LOW selects an access cycle for
WORD WRITE
RAS#
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED
DATA
0
0
1
0
0
0
0
0
STORED
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
UPPER BYTE
(DQ8-DQ15)
OF WORD
0
1
0
1
0
0
0
0
X
X
X
X
X
X
X
X
ADDRESS 0
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
ADDRESS 1
1
0
1
0
1
1
1
1
X = NOT EFFECTIVE (DON'T CARE)
Figure 1
WORD and BYTE WRITE Example
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
DRAM ACCESS (continued)
the upper byte (DQ8-DQ15). General byte and word
access timing is shown in Figures 1 and 2.
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE or CAS# (CASL# or CASH#), whichever occurs
last. An EARLY WRITE occurs when WE is taken LOW
prior to either CAS# falling. A LATE WRITE or READ-
MODIFY-WRITE occurs when WE falls after CAS# (CASL#
or CASH#) is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of
the state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the
data outputs prior to applying input data. If a LATE
WRITE or READ-MODIFY-WRITE is attempted while
keeping OE# LOW, no write will occur, and the data
outputs will drive read data from the accessed location.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For
example, an EARLY WRITE on one byte and a LATE
WRITE on the other byte are not allowed during the
same cycle. However, an EARLY WRITE on one byte and
a LATE WRITE on the other byte, after a CAS# precharge
has been satisfied, are permissible.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 64Mb EDO
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO, and it allows CAS# precharge time (
t
CP) to
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).
EDO operates like any DRAM READ or FAST-PAGE-
MODE READ, except data is held valid after CAS# goes
HIGH, as long as RAS# and OE# are held LOW and WE#
is held HIGH. OE# can be brought LOW or HIGH while
CAS# and RAS# are LOW, and the DQs will transition
between valid data and High-Z. Using OE#, there are
WORD READ
RAS#
LOWER BYTE READ
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
OUTPUT
DATA
1
1
0
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
UPPER BYTE
(DQ8-DQ15)
OF WORD
ADDRESS 0
Z = High-Z
ADDRESS 1
Figure 2
WORD and BYTE READ Example
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
RAS#
V IH
V IL
CAS#
V IH
V IL
ADDR
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH
V IOL
OPEN
VALID DATA (A)
tOD
tOES
VALID DATA (A)
VALID DATA (B)
tOD
tOEHC
VALID DATA (C)
tOD
VALID DATA (D)
OE#
V IH
V IL
tOE
tOEP
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEP is met.
Figure 3
OE# Control of DQs
RAS#
V IH
V IL
CAS#
V IH
V IL
ADDR
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH
V IOL
OPEN
VALID DATA (A)
tWHZ
VALID DATA (B)
tWHZ
INPUT DATA (C)
WE#
V IH
V IL
V IH
V IL
tWPZ
OE#
The DQs go to High-Z if WE# falls and, if
t
WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 4
WE# Control of DQs
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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