XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
JULY 2006
REV. 1.0.4
GENERAL DESCRIPTION
The XRT75L04 is a four-channel fully integrated Line
Interface Unit (LIU) with Jitter Attenuator for E3/DS3/
STS-1 applications. It incorporates four independent
Receivers, Transmitters and Jitter Attenuators in a
single 176 pin LQFP package.
Each channel of the XRT75L04 can be configured to
operate in E3 (34.368 MHz), DS3 (44.736 MHz) or
STS-1 (51.84 MHz) rates that are independent of
each other. Each transmitter can be turned off and tri-
stated for redundancy support and for conserving
power.
The XRT75L04’s differential receivers provide high
noise interference margin and are able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L04 incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Telcordia GR-499, GR-253 specifications.
The XRT75L04 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L04 supports local, remote and digital
loop-backs. The XRT75L04 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
•
Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
TRANSMITTER:
•
Compliant with Telcordia GR-499, GR-253 and
ANSI T1.102 Specification for transmit pulse
•
Tri-state Transmit output capability for redundancy
applications
•
Transmitters can be turned on or off.
JITTER ATTENUATOR:
•
On chip advanced crystal-less Jitter Attenuator.
•
Jitter Attenuators can be selected in Receive or
Transmit paths.
•
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-253 and GR-499-
CORE,1995 standards.
•
Meets ETSI TBR 24 Jitter Transfer Requirements.
•
16 or 32 bits selectable FIFO size.
•
Meets the Wander specifications described in
T1.105.03b.
•
Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
•
Serial Microprocessor Interface for control and
configuration.
•
Supports
Monitoring.
optional
internal
Transmit
Driver
FEATURES
RECEIVER:
•
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
•
Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
•
Detects and Clears LOS as per G.775.
•
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
•
PRBS error counter register to accumulate errors.
•
Supports Local, Remote and Digital Loop-backs.
•
Single 3.3 V ± 5% power supply.
•
5 V Tolerant I/O.
•
Maximum Power Dissipation 1.5W.
•
Available in 176 pin LQFP package
•
- 40°C to 85°C Industrial Temperature Range.
APPLICATIONS
•
E3/DS3 Access Equipment.
•
STS1-SPE to DS3 Mapper.
•
DSLAMs.
•
Digital Cross Connect Systems.
•
CSU/DSU Equipment.
•
Routers.
•
On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
•
On-chip
clock
synthesizer
generates
the
appropriate rate clock from a single frequency
XTAL.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT 75L04
REV. 1.0.4
SDI
SDO
INT
SClk
CS
RESET
HOST/HW
STS-1/DS3_(n)
E3_(n)
REQEN_(n)
RTIP_(n)
RRing_(n)
SR/DR
LLB_(n)
Serial
Processor
Interface
XRT75L04
XRT75L04
CLKOUT
E3Clk,DS3Clk,
STS-1Clk
RLOL_(n)
RxON
RxClkINV
Peak Detector
Slicer
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
Attenuator
Invert
HDB3/
B3ZS
Decoder
RxClk_(n)
RPOS_(n)
RNEG_(n)/
LCV_(n)
AGC/
Equalizer
MUX
Local
LoopBack
Remote
LoopBack
RLB_(n)
RLOS_(n)
JATx/Rx
TPData_(n)
TNData_(n)
TxClk_(n)
TAOS_(n)
TxLEV_(n)
TTIP_(n)
TRing_(n)
MTIP_(n)
MRing_(n)
DMO_(n)
Line
Driver
Tx
Pulse
Shaping
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Device
Monitor
Tx
Control
Channel 0
Channel 1..2
Channel 3
TxON_(n)
Notes: 1. (n) = 0, 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
•
Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
•
Integrated Pulse Shaping Circuit.
•
Built-in B3ZS/HDB3 Encoder (which can be disabled).
•
Accepts Transmit Clock with duty cycle of 30%-70%.
•
Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.
•
Generates pulses that comply with the DSX-3 pulse template, as specified in Telcordia GR-499
-CORE
and
ANSI T1.102_1993.
•
Generates pulses that comply with the STSX-1 pulse template, as specified in Telcordia GR-253-CORE.
•
Transmitters can be turned off to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
•
Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.
•
Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.
•
Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.
•
Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.
•
Built-in B3ZS/HDB3 Decoder (which can be disabled).
•
Recovered Data can be muted while the LOS Condition is declared.
2
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
•
Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment.
F
IGURE
2. P
IN
O
UT OF THE
XRT75L04
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
TEST
ICT
REQEN_2
E3_2
STS1/DS3_2
LLB_2
RLB_2
RxAVDD_2
RRING_2
RTIP_2
RxAGND_2
REQEN_3
E3_3
STS1/DS3_3
LLB_3
RLB_3
RxAVDD_3
RRING_3
RTIP_3
RxAGND_3
RefAGND
RxA
RxB
RefAVDD_1
RxAGND_1
RTIP_1
RRING_1
RxAVDD_1
RLB_1
LLB_1
STS1/DS3_1
E3_1
REQEN_1
RxAGND_0
RTIP_0
RRING_0
RxAVDD_0
RLB_0
LLB_0
STS1/DS3_0
E3_0
REQEN_0
AGND
AGND
RESET
HOST/HW
NC
SR/DR
NC
RLOS_2
RLOL_2
DGND_2
RPOS_2
RNEG/LCV_2
RxCLK_2
DVDD_2
RLOS_3
RLOL_3
DGND_3
RPOS_3
RNEG/LCV_3
RxCLK_3
DVDD_3
TxMON
JA0
JA1
JATx/Rx
SFM_EN
JaDVDD_3
CLKOUT_3
JaDGND_3
JaDGND_2
CLKOUT_2
JaDVDD_2
JaAVDD_2
CLKOUTEN_2
JaAGND_2
JaAGND_3
CLKOUTEN_3
JaAVDD_3
TxON_2
TAOS_2
TxLEV_2
TxON_3
TAOS_3
TxLEV_3
TxCLK_2
TPOS_2
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
XRT75L04
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
SCLK/TxCLKINV
SDI/RxON
CS/RxCLKINV
SDO/RxMON
INT/LOSMUT
RLOS_0
RLOL_0
DGND_0
RPOS_0
RNEG/LCV_0
RxCLK_0
DVDD_0
RLOS_1
RLOL_1
DGND_1
RPOS_1
RNEG/LCV_1
RxCLK_1
DVDD_1
E3CLK
CLKVDD
DS3CLK
CLKGND
STS1CLK/12M
JaDVDD_1
CLKOUT_1
JaDGND_1
JaDGND_0
CLKOUT_0
JaDVDD_0
JaAVDD_0
CLKOUTEN_0
JaAGND_0
JaAGND_1
CLKOUTEN_1
JaAVDD_1
TxON_0
TAOS_0
TxLEV_0
TxON_1
TAOS_1
TxLEV_1
TxCLK_0
TPOS_0
P
ART
N
UMBER
XRT75L04IV
TNEG_2
TxAVDD_2
DMO_2
TTIP_2
TxVDD_2
TRING_2
TxGND_2
MTIP_2
MRING_2
TxAGND_2
TxCLK_3
TPOS_3
TNEG_3
TxAVDD_3
DMO_3
TTIP_3
TxVDD_3
TRING_3
TxGND_3
MTIP_3
MRING_3
TxAGND_3
TxAGND_1
MRING_1
MTIP_1
TxGND_1
TRING_1
TxVDD_1
TTIP_1
DMO_1
TxAVDD_1
TNEG_1
TPOS_1
TxCLK_1
TxAGND_0
MRING_0
MTIP_0
TxGND_0
TRING_0
TxVDD_0
TTIP_0
DMO_0
TxAVDD_0
TNEG_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ORDERING INFORMATION
P
ACKAGE
176 Pin LQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
3
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
F
EATURES
.....................................................................................................................................................1
A
PPLICATIONS
................................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT 75L04 .............................................................................................................................. 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
........................................................................................................2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................................2
F
IGURE
2. P
IN
O
UT OF THE
XRT75L04............................................................................................................................................ 3
ORDERING INFORMATION.....................................................................................................................3
T
ABLE OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................4
T
RANSMIT
I
NTERFACE
.....................................................................................................................................4
R
ECEIVE
I
NTERFACE
.......................................................................................................................................7
C
LOCK
I
NTERFACE
.........................................................................................................................................9
C
ONTROL AND
A
LARM
I
NTERFACE
.................................................................................................................10
O
PERATING
M
ODE
S
ELEC
T ..........................................................................................................................12
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
.........................................................................................................12
J
ITTER
A
TTENUATOR INTERFACE
...................................................................................................................13
A
NALOG
P
OWER AND
G
ROUND
.....................................................................................................................14
DIGITAL
P
OWER AND
G
ROUND
......................................................................................................................16
1.0 ELECTRICAL CHARACTERISTICS ....................................................................................................17
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
......................................................................................................................................... 17
T
ABLE
2: DC E
LECTRICAL
C
HARACTERISTICS
: ................................................................................................................................ 17
2.0 TIMING CHARACTERISTICS ..............................................................................................................18
F
IGURE
3.
F
IGURE
4.
F
IGURE
5.
F
IGURE
6.
T
YPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE
XRT75L04 (
DUAL
-
RAIL DATA
)........................................... 18
T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
.......................................................................................................................... 18
R
ECEIVER
D
ATA OUTPUT AND CODE VIOLATION TIMING
................................................................................................... 19
T
RANSMIT
I
NTERFACE CIRCUIT FOR
E3, DS3
AND
STS-1 R
ATES
.................................................................................... 19
3.0 LINE SIDE CHARACTERISTICS: ........................................................................................................20
3.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 20
F
IGURE
7. P
ULSE
M
ASK FOR
E3 (34.368
MBITS
/
S
)
INTERFACE AS PER ITU
-
T
G.703......................................................................... 20
T
ABLE
3: E3 T
RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
........................................................ 20
F
IGURE
8. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
SONET STS-1 A
PPLICATIONS
............................. 21
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
..................................................................................................................................... 21
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) .............................. 22
F
IGURE
9. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE FOR
DS3
AS PER
B
ELLCORE
GR-499 ..................................................................... 22
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................ 23
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ................................. 23
F
IGURE
10. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
S
TRUCTURE
...................................................................................................... 24
F
IGURE
11. T
IMING
D
IAGRAM FOR THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 24
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND LOAD
= 10
P
F) .................................. 25
4.0 THE TRANSMITTER SECTION: ..........................................................................................................26
F
IGURE
12. S
INGLE
-R
AIL OR
NRZ D
ATA
F
ORMAT
(E
NCODER AND
D
ECODER ARE
E
NABLED
)............................................................ 26
F
IGURE
13. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER AND DECODER ARE DISABLED
) ............................................................................. 26
4.1 TRANSMIT CLOCK: ....................................................................................................................................... 26
4.2 B3ZS/HDB3 ENCODER: ................................................................................................................................. 26
4.2.1 B3ZS ENCODING: ...................................................................................................................................................... 26
F
IGURE
14. B3ZS E
NCODING
F
ORMAT
........................................................................................................................................... 27
4.2.2 HDB3 ENCODING:...................................................................................................................................................... 27
F
IGURE
15. HDB3 E
NCODING
F
ORMAT
.......................................................................................................................................... 27
4.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 27
4.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 28
4.3.2 INTERFACING TO THE LINE: .................................................................................................................................... 28
4.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 28
F
IGURE
16. T
RANSMIT
D
RIVER
M
ONITOR SET
-
UP
. ........................................................................................................................... 28
4.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 30
5.0 THE RECEIVER SECTION: .................................................................................................................30
5.1 AGC/EQUALIZER: .......................................................................................................................................... 30
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 31
I
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
F
IGURE
17. I
NTERFERENCE
M
ARGIN
T
EST
S
ET UP FOR
DS3/STS-1................................................................................................ 31
F
IGURE
18. I
NTERFERENCE
M
ARGIN
T
EST
S
ET UP FOR
E3. ............................................................................................................ 32
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
........................................................................................................................... 32
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 32
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 32
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 33
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 33
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION AND
C
LEARANCE
T
HRESHOLDS FOR A GIVEN SETTING OF
REQEN (DS3
AND
STS-
1 A
PPLICATIONS
) ............................................................................................................................................................ 33
D
ISABLING
ALOS/DLOS D
ETECTION
: .......................................................................................................... 33
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 33
F
IGURE
19. L
OSS
O
F
S
IGNAL
D
EFINITION FOR
E3
AS PER
ITU-T G.775.......................................................................................... 34
F
IGURE
20. L
OSS OF
S
IGNAL
D
EFINITION FOR
E3
AS PER
ITU-T G.775. ......................................................................................... 34
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 35
6.0 JITTER: ................................................................................................................................................ 36
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 36
F
IGURE
21. J
ITTER
T
OLERANCE
M
EASUREMENTS
........................................................................................................................... 36
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 36
F
IGURE
22. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1................................................................................................................ 37
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 37
F
IGURE
23. I
NPUT
J
ITTER
T
OLERANCE FOR
E3 .............................................................................................................................. 37
T
ABLE
11: J
ITTER
A
MPLITUDE VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) .................................................................. 38
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 38
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
............................................................................................................ 38
6.3 JITTER GENERATION: .................................................................................................................................. 38
6.4 JITTER ATTENUATOR: ................................................................................................................................. 38
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
.................................................................................................................................... 39
F
IGURE
24. J
ITTER
T
RANSFER
R
EQUIREMENTS AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
................................................................ 39
7.0 SERIAL HOST INTERFACE: ............................................................................................................... 40
T
ABLE
14:
T
ABLE
15:
T
ABLE
16:
T
ABLE
17:
T
ABLE
18:
T
ABLE
19:
T
ABLE
20:
T
ABLE
21:
F
UNCTIONS OF SHARED PINS
......................................................................................................................................... 40
R
EGISTER
M
AP AND
B
IT
N
AMES
.................................................................................................................................... 40
R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
......................................................................................................................... 41
R
EGISTER
M
AP AND
B
IT
N
AMES
- C
HANNEL
0 R
EGISTERS
.............................................................................................. 42
R
EGISTER
M
AP AND
B
IT
N
AMES
- C
HANNEL
1 R
EGISTERS
.............................................................................................. 42
R
EGISTER
M
AP AND
B
IT
N
AMES
- C
HANNEL
2 R
EGISTERS
.............................................................................................. 43
R
EGISTER
M
AP AND
B
IT
N
AMES
- C
HANNEL
3 R
EGISTERS
.............................................................................................. 43
R
EGISTER
M
AP
D
ESCRIPTION
........................................................................................................................................ 44
8.0 DIAGNOSTIC FEATURES: ................................................................................................................. 49
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 49
F
IGURE
25. PRBS MODE ............................................................................................................................................................. 49
8.2 LOOPBACKS: ................................................................................................................................................ 49
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 49
F
IGURE
26. A
NALOG
L
OOPBACK
..................................................................................................................................................... 50
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 50
F
IGURE
27. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 50
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 51
F
IGURE
28. R
EMOTE
L
OOPBACK
.................................................................................................................................................... 51
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 51
F
IGURE
29. T
RANSMIT
A
LL
O
NES
(TAOS)...................................................................................................................................... 51
APPENDIX B .................................................................................................................... 52
T
ABLE
22: TRANSFORMER RECOMMENDATIONS .................................................................................................................. 52
T
ABLE
23: T
RANSFORMER
D
ETAILS
................................................................................................................................................ 52
ORDERING INFORMATION .................................................................................................................. 54
P
ACKAGE
D
IMENSIONS
- 176
PIN PACKAGE
.................................................................................................. 54
R
EVISIONS
................................................................................................................................................... 55
II
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