AD7894: 5V, 14-Bit Serial, 5 us ADC in S0-8 Package Data
Sheet
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TOOLS AND SIMULATIONS
•
AD7894 IBIS Model
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number.
REFERENCE MATERIALS
Technical Articles
•
MS-2210: Designing Power Supplies for High Speed ADC
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AD7894–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
2
Signal to (Noise + Distortion) Ratio
3
@ +25°C
T
MIN
to T
MAX
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise
3
Intermodulation Distortion (IMD)
3
2nd Order Terms
3rd Order Terms
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Relative Accuracy
3
Differential Nonlinearity
3
AD7894-2
Positive Gain Error
3
Unipolar Offset Error
AD7894-10, AD7894-3 Only
Positive Gain Error
3
Negative Gain Error
3
Bipolar Zero Error
ANALOG INPUT
AD7894-10
Input Voltage Range
Input Current
AD7894-3
Input Voltage Range
Input Current
AD7894-2
Input Voltage Range
Input Current
REFERENCE INPUT
REF IN Input Voltage Range
Input Current
Input Capacitance
4
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output Coding
AD7894-10, AD7894-3
AD7894-2
CONVERSION RATE
Conversion Time
Mode 1 Operation
Mode 2 Operation
5
Track/Hold Acquisition Time
3
SAMPLE AND HOLD
–3 dB Small Signal Bandwidth
Aperture Jitter
A Versions
l
78
77
–86
–92
–92
–92
14
14
±
2
–1 to +1.5
±
12
±
8
±
8
±
8
±
10
(V
DD
= +5 V 5%, GND = 0 V, REF IN = +2.5 V. All specifications T
MIN
to T
MAX
unless
otherwise noted.)
B Versions
1
Units
Test Conditions/Comments
78
77
–86
–92
–92
–92
14
14
±
1.5
–1 to +1.5
±
10
±
6
±
6
±
6
±
8
dB min
dB min
dB max
dB typ
dB typ
dB typ
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
f
IN
= 70 kHz Sine Wave, f
SAMPLE
= 160 kHz
See Figure 14
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 160 kHz,
Typically –87 dB. See Figure 15
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 160 kHz
fa = 9 kHz, fb
=
9.5 kHz, f
SAMPLE
= 160 kHz
±
10
2
±
2.5
1.5
0 to +2.5
500
2.375/2.625
1
10
2.4
0.8
±
10
10
4.0
0.4
±
10
2
±
2.5
1.5
0 to +2.5
500
2.375/2.625
1
10
2.4
0.8
±
10
10
4.0
0.4
V
mA max
V
mA max
V
nA max
V min/V max
µA
max
pF max
V min
V max
µA
max
pF max
V min
V max
See Analog Input Section
See Analog Input Section
2.5 V
±
5%
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
I
SOURCE
= 400
µA
I
SINK
= 1.6 mA
Twos Complement
Straight (Natural) Binary
5
10
0.35
7.5
50
5
10
0.35
7.5
50
µs
max
µs
max
µs
max
MHz typ
ps typ
–2–
REV. 0
AD7894
Parameter
POWER REQUIREMENTS
V
DD
I
DD
Power Dissipation
Power-Down Mode
I
DD
@ T
MIN
to T
MAX
Power Dissipation T
MIN
to T
MAX
A Versions
l
+5
5.5
27.5
20
100
B Versions
1
Units
+5
5.5
27.5
20
100
V nom
mA max
mW max
µA
max
µW
max
Test Conditions/Comments
±
5% for Specified Performance
Digital Inputs @ V
DD
, V
DD
= 5 V
±
5%
Typically 20 mW
Digital Inputs @ GND, V
DD
= 5 V
±
5%
Typ 15
µW
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C.
2
Applies to Mode 1 operation. See Operating Modes section.
3
See Terminology.
4
Sample tested @ +25°C to ensure compliance.
5
This 10
µs
includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of
CONVST,
whereas conversion is timed from the falling
edge of
CONVST,
for narrow
CONVST
pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10
µs.
This can be seen from
Figure 3. Note that if the
CONVST
pulsewidth is greater than 5
µs,
the effective conversion time will increase beyond 10
µs.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
A, B Versions
40
31.25
2
31.25
2
60
3
10
20
4
DD
= +5 V
5%, GND = 0 V, REF IN = +2.5 V)
Units
ns min
ns min
ns min
ns max
ns min
ns max
Test Conditions/Comments
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
Data Access Time after Falling Edge of SCLK
V
DD
= 5 V
±
5%
Data Hold Time after Falling Edge of SCLK
Bus Relinquish Time after Falling Edge of SCLK
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t
4
, and the setup time required for the user’s
processor. These two times will determine the maximum SCLK frequency with which the user’s system can operate. See Serial Interface section for more information.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
6
, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
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